# RegisterMap for m\_axi HLS IP and a HLS version comparison case

**URL:** <https://discuss.pynq.io/t/registermap-for-m-axi-hls-ip-and-a-hls-version-comparison-case/6430>\
**Category:** Support\
**Created:** [December 10, 2023, 8:21pm UTC](https://discuss.pynq.io/t/registermap-for-m-axi-hls-ip-and-a-hls-version-comparison-case/6430 "2023-12-10T20:21:36Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![AllenChenChao](https://avatars.discourse-cdn.com/v4/letter/a/7bcc69/32.png) [@AllenChenChao](https://discuss.pynq.io/u/AllenChenChao)\
**Post date:** [December 10, 2023, 8:21pm UTC](https://discuss.pynq.io/t/registermap-for-m-axi-hls-ip-and-a-hls-version-comparison-case/6430/1 "2023-12-10T20:21:36Z")

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Hi, I want to achieve axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2. I meet some problem and feel confusing when using register map.

**Target:**

1. axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2
2. know more about FPGA and axi

**Environment:**  
Pynq-Z1  
Vivado 2019.1 Vivado HLS 2019.1 vs Vivado 2021.2, Vitis HLS 2021.2

**Operations with Vivado (HLS) 2019.1:**  
Step on blog [axi4](https://pp4fpgas.readthedocs.io/en/latest/axi4.html).  
**Result:**  
HW IP works well in [AXI Burst works well on Pynq Z1/Z2 with Vivado HLS](https://discuss.pynq.io/t/axi-burst-need-support-on-pynq-z1-z2-with-vitis-hls-rather-than-merely-vivado-hls/6413):

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/7/7dc7b309f5dcb87aebc9c006a6aa24c874c94165.png)

**Operations with Vitis HLS and Vivado2021.2:**  
Step on blog [axi4](https://pp4fpgas.readthedocs.io/en/latest/axi4.html) again.  
**Result:**

1. Unlike in version 2019.1, there is double in and out in version 2021.2.
2. HW IP seems not work in my operations。  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/2b336575c98972da82c5c6febf73cd70ac8a8b72.png)

I checked the [AXI4 Master Interface](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/AXI4-Master-Interface), it will take me some time to figure it out.  
At the same time, may I ask if there would be a right way to use HW IP on Pynq.

Here is the interface:

```auto
#pragma HLS INTERFACE s_axilite port=return bundle=sqrt
#pragma HLS INTERFACE s_axilite port=len bundle=sqrt
#pragma HLS INTERFACE m_axi depth=100 port=out offset=slave bundle=output
#pragma HLS INTERFACE m_axi depth=100 port=in offset=slave bundle=input
#pragma HLS INTERFACE s_axilite port=in bundle=sqrt
#pragma HLS INTERFACE s_axilite port=out bundle=sqrt

```

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<div class="post-metadata">

**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [February 13, 2024, 11:33am UTC](https://discuss.pynq.io/t/registermap-for-m-axi-hls-ip-and-a-hls-version-comparison-case/6430/2 "2024-02-13T11:33:45Z")

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The default settings and behaviour of HLS can change over the different versions.

The number of registers generated depends on the size of the data. If you have a 32 bit value, you will only have one register. 64 bit = 2 registers. You will also see this difference if you move from a Zynq 7000 (32-bit) design to a Zynq Ultrascale+ (64 bit) or if you set the size of your data bus to these widths in different designs.

Cathal

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<div class="post-metadata">

**Author:** ![system](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/system/32/2_2.png) [@system](https://discuss.pynq.io/u/system)\
**Post date:** [December 21, 2025, 5:01am UTC](https://discuss.pynq.io/t/registermap-for-m-axi-hls-ip-and-a-hls-version-comparison-case/6430/3 "2025-12-21T05:01:54Z")

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