# RFDC Start Up Fail - ADC 0 timed out at state 7 in XRFdc\_WaitForRestartClr **URL:** \ **Category:** Support\ **Created:** [May 22, 2024, 4:19pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042 "2024-05-22T16:19:18Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [May 22, 2024, 4:19pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/1 "2024-05-22T16:19:18Z")
Hi, I am trying to use PLL of RFDC in RFSoC4x2 board. In my design, I try to capture RF data from both channels of ADC0 Tile 224 (ADC C & ADC D in RFSoC 4x2 reference manual). Clock configuration for RFDC is given below: ![Screenshot 2024-05-22 120031](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/8fa00bf1dd2918a39aaf7413678dc7edf5607b16.png) Before adding PLL to design, I was able to capture data without any issues. When PLL is added to design, my RFDC can’t startup. When I try to startup or reset I get the following error : `"RuntimeError: Function XRFDC_StartUP call failed stdout: metal: error: ADC 0 timed out at state 7 in XRFdc_WaitForRestartClr"` I couldn’t find what exactly state 7 means. If you could help me with this issue and point to documentation about state errors, I would be grateful. PYNQ version:3.0.1 Board: RFSoC 4x2 Thanks ---
**Author:** ![godfly](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/godfly/32/4074_2.png) [@godfly](https://discuss.pynq.io/u/godfly)\ **Post date:** [December 17, 2024, 4:55pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/2 "2024-12-17T16:55:08Z")
I’m getting the same error. I guess it’s due to the reference clock in IP configuration not matching the lmk and lmx clocks on the board. By default they are set by `xrfclk.set_ref_clks(lmk_freq=245.76, lmx_freq=491.52)`. One needs to change this using a tool provided by TI, as stated in the RFSoC4x2 reference manual. ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [December 18, 2024, 2:06pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/3 "2024-12-18T14:06:20Z")
Thanks for the reply! I was afraid to go down that road to be honest. But, I will check it out. Please, let me know if it works out using the tool. Best ---
**Author:** ![godfly](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/godfly/32/4074_2.png) [@godfly](https://discuss.pynq.io/u/godfly)\ **Post date:** [December 18, 2024, 6:19pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/4 "2024-12-18T18:19:20Z")
I set the reference clock to 409.6MHz, and used `xrfclk.set_ref_clks(lmk_freq=245.76, lmx_freq=409.6)`, and now it works. The point is to make sure the LMX clock is the same as the reference clock in the IP configuration for the RFDC. Otherwise, the `rfdc.adc_tiles[0].StartUp()` command would fail because you are basically providing wrong clocks to the rfdc (I guess). However, if you want a clock frequency which is a multiple of 1000 (say, 300MHz, as in your design) rather than a multiple of 1024 (say, 491.52MHz or 409.6MHz), then you might consider using the register file provided [here](https://github.com/Xilinx/RFSoC-MTS/tree/main/boards/RFSoC4x2/xrfclk), which set both LMK and LMX clock to 500MHz. If 500MHz is not an option for your reference clock in the IP config, then you might have to design your own register file using the [TICSPRO software](https://www.ti.com/tool/TICSPRO-SW), which I failed because I don’t know much about the LMK and LMX chips. ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [December 19, 2024, 5:25pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/5 "2024-12-19T17:25:40Z")
Thanks for the advice! It is really helpfu!😃 I am dealing with a different part of the project right now. I will let you know if it works! Best ---
**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\ **Post date:** [February 19, 2025, 4:22pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/6 "2025-02-19T16:22:22Z")
Hi godfly, I tried the changed the registers using TICS PRO software. You were right about clocks (state 7 error caused by clock issues). I believe it is working correctly, but my PLL Lock LED indicators don’t turn on. I have created a new topic about it in the [RFSoC 4x2 PLL Lock Leds don’t turn on](https://discuss.pynq.io/t/rfsoc-4x2-pll-lock-leds-dont-turn-on/8063) Hope, you were able to resolve your issue as well. Best ---
**Author:** ![system](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/system/32/2_2.png) [@system](https://discuss.pynq.io/u/system)\ **Post date:** [April 24, 2025, 1:51pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/7 "2025-04-24T13:51:35Z")
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