# RFDC Start Up Fail - ADC 0 timed out at state 7 in XRFdc\_WaitForRestartClr

**URL:** <https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042>\
**Category:** Support\
**Created:** [May 22, 2024, 4:19pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042 "2024-05-22T16:19:18Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![godfly](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/godfly/32/4074_2.png) [@godfly](https://discuss.pynq.io/u/godfly)\
**Post date:** [December 18, 2024, 6:19pm UTC](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042/4 "2024-12-18T18:19:20Z")

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I set the reference clock to 409.6MHz, and used `xrfclk.set_ref_clks(lmk_freq=245.76, lmx_freq=409.6)`, and now it works.

The point is to make sure the LMX clock is the same as the reference clock in the IP configuration for the RFDC. Otherwise, the `rfdc.adc_tiles[0].StartUp()` command would fail because you are basically providing wrong clocks to the rfdc (I guess).

However, if you want a clock frequency which is a multiple of 1000 (say, 300MHz, as in your design) rather than a multiple of 1024 (say, 491.52MHz or 409.6MHz), then you might consider using the register file provided [here](https://github.com/Xilinx/RFSoC-MTS/tree/main/boards/RFSoC4x2/xrfclk), which set both LMK and LMX clock to 500MHz. If 500MHz is not an option for your reference clock in the IP config, then you might have to design your own register file using the [TICSPRO software](https://www.ti.com/tool/TICSPRO-SW), which I failed because I don’t know much about the LMK and LMX chips.

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_[View the full topic](https://discuss.pynq.io/t/rfdc-start-up-fail-adc-0-timed-out-at-state-7-in-xrfdc-waitforrestartclr/7042)._