# RFSoC 4x2: How to locked clk\_in0 to dout8 through LMK04828 and then give to FPGA PL SYS REFCLK?

**URL:** <https://discuss.pynq.io/t/rfsoc-4x2-how-to-locked-clk-in0-to-dout8-through-lmk04828-and-then-give-to-fpga-pl-sys-refclk/8282>\
**Category:** Support\
**Created:** [April 7, 2025, 6:41am UTC](https://discuss.pynq.io/t/rfsoc-4x2-how-to-locked-clk-in0-to-dout8-through-lmk04828-and-then-give-to-fpga-pl-sys-refclk/8282 "2025-04-07T06:41:09Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Xinyuan](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/xinyuan/32/6830_2.png) [@Xinyuan](https://discuss.pynq.io/u/Xinyuan)\
**Post date:** [April 7, 2025, 6:41am UTC](https://discuss.pynq.io/t/rfsoc-4x2-how-to-locked-clk-in0-to-dout8-through-lmk04828-and-then-give-to-fpga-pl-sys-refclk/8282/1 "2025-04-07T06:41:09Z")

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I need to give a external 80MHz sine wave to clkin0 as a reference clock, and use PLLs in LMK04828 to divide 320MHz clock for FPGA and ADC. I want all the clock (including FPGA and ADC) can keep in synchronization with the external 80MHz sine wave signal.  
But when I cut off the external clkin0, the fpga still have reference clock (but have no sysref), so how to locked clk\_in0 to dout8 through LMK04828 and then give to FPGA PL SYS REFCLK?

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**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\
**Post date:** [April 8, 2025, 2:34am UTC](https://discuss.pynq.io/t/rfsoc-4x2-how-to-locked-clk-in0-to-dout8-through-lmk04828-and-then-give-to-fpga-pl-sys-refclk/8282/2 "2025-04-08T02:34:12Z")

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Hi,

You need to use TICS PRO software to change the internal clockings of LMK04828 and LMX2594.

Best