# RFSoC 4x2 issue with POWER SEQUENCING

**URL:** https://discuss.pynq.io/t/rfsoc-4x2-issue-with-power-sequencing/7286
**Category:** Support
**Created:** [July 17, 2024, 10:36am UTC](https://discuss.pynq.io/t/rfsoc-4x2-issue-with-power-sequencing/7286 "2024-07-17T10:36:03Z")
**Posts on this page:** 1
**Page:** 1

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### Author: ![ireliashallnotfall](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/ireliashallnotfall/32/6186_2.png) [@ireliashallnotfall](https://discuss.pynq.io/u/ireliashallnotfall)
#### Post date: [July 17, 2024, 10:36am UTC](https://discuss.pynq.io/t/rfsoc-4x2-issue-with-power-sequencing/7286/1 "2024-07-17T10:36:03Z")

</div>

Hi Everyone,According to the RFSoC 4x2 schematic I downloaded from website . I found Power-Up Sequence seems not right .  
According to MT40A512M16LY-062E datasheet ,

 ![1721209054754_CA3B0490-CC60-4b07-A0EF-26F4E4C7B3A1](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/297dacbb7205abe776b3f0a6c2e57ff649d52ad9.png)  
VPP followed by VDD and VDDQ . On RFSoC 4x2 schematic page 45 ,it become VDD and VDDQ followed by VPP. Is it right?  
Thank you