RFSoC Single DAC

Hi, I have been studying the pynq rfsoc examples out there ( QPSK, Spectrum Analizer … ) and I have seen that there are no examples ( that I have found ) of simply using the DAC of the card to transmit some user defined values (like an AWG), either at a higher level ( generate these values in PS and then transmit them to the PL by DMA ) or generate them directly in PL. I would like to know if there is any example or documentation to do this with PYNQ RFSOC.

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Hi @Allanos,

Welcome to the PYNQ community.

I suggest you check the DMA tutorials:


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Hi Mario,

Thanks for sending me the tutorials, I will look at them carefully !
I understand that these are for the DMA part, but for the rf data converters part, what documentation do I have to look at ?

I imagine that part is controlled by the xrfdc driver, but I haven’t seen much documentation nor found any example about it in python.

Thank you very much

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The Multi-Tile Synchronization Example is better than the default example for things like streaming raw samples to and from memory:

Sure it synchronizes the tiles, but it’s also a relatively simple example of loading 64 kilosamples worth of real samples from a numpy array into an internal RAM (BRAM or URAM inside of the FPGA fabric) and then feeding these samples to a DAC over and over again at 4 GSPS.

I’ve played with the project in Vivado and it’s not that hard to do things like:

  • increase the internal RAM size for DAC and ADC (only up to a few factors of 2 until you run out of room)
  • make two independent, synchronized DAC channels (through the magic of copy and paste)
  • change the number of samples that get streamed before it repeats (to stream less than exactly the RAM size, but only as long as it’s a multiple of something like 16 samples or whatever the number that get fed in parallel is).
  • feed Verilog-generated samples rather than samples read out of the internal RAM (I only started to look into this, but ended up being fine with precomputing things. Again, you’d need to compute something like the next 16 samples at each clock cycle.)

There is also a Direct memory access (DMA) part of this example, which captures ADC samples into a few gigabytes of DRAM. I haven’t played with this part of the project, but if you need more than ~1M samples streamed to your DAC, this might be a reasonable starting point to looks at. You’d need to reverse the DMA direction for DAC instead of ADC.