# RFSoC4x2 Register Map Different Format

**URL:** <https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702>\
**Category:** Support\
**Created:** [September 26, 2022, 8:30pm UTC](https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702 "2022-09-26T20:30:08Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![JennySmith888](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jennysmith888/32/1966_2.png) [@JennySmith888](https://discuss.pynq.io/u/JennySmith888)\
**Post date:** [September 26, 2022, 8:30pm UTC](https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702/1 "2022-09-26T20:30:08Z")

</div>

Hi,

I am attempting to port a working ZCU111 design to the RFSoC4x2. I am seeing some discrepancy in the register map entries in my Jupyter Notebook across the boards which is causing all of my custom IP drivers to break on the 4x2. Both boards are running PYNQv2.7 and the hwh file entries for the registers I’m trying to access look identical. I’m not sure where the discrepancy is coming from or how to fix it. See details below.

Both designs were built with Vivado 2022.1 using HLS IP exported from Vitis HLS 2021.1 and integrated using an IP Integrator flow. For example, when I try to access the `run` register in my `dac_table` IP I see the correct thing on the ZCU111:

```auto
ol.dac_table.register_map.run
Register(run=0, RESERVED=0)

```

When I try this on the RFSoC4x2 I see:

```auto
ol.dac_table.register_map.run
Register(run=write-only, RESERVED=write-only)

```

Which breaks the driver… Both designs have identical entries for this register in the `.hwh`:

```auto
<REGISTER NAME="run">
              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of run"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="52"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
              <FIELDS>
                <FIELD NAME="run">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 0 to 0 of run"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>

```

As a side note despite being “write only” the register is able to be read properly on the ZCU111 and I see the run bit turn to 1 as it should when the IP is running.

Both boards are running PYNQ v2.7.0 git id: 285d1457e64c076bbb39844afd54b38f075ad2c7. If anyone has advice for where I can track down the source of this issue please let me know.

**Build / Reproduce Instructions:**  
The design is buildable for the ZCU111 and the RFSoC4x2 in Vivado 2022.1.

Build ZCU111:

```auto
git clone -b 2022.1 https://github.com/MazinLab/gen3-vivado-top.git --recurse-submodules
cd gen3-vivado-top
source <Vivado path>
make gen3_top

```

Build RFSoC4x2:

```auto
git clone -b rfsoc4x2 https://github.com/MazinLab/gen3-vivado-top.git --recurse-submodules
cd gen3-vivado-top
source <Vivado path>
make gen3_top

```

To run the design on a board you must download the python package:  
In a terminal on a RFSoC4x2 or ZCU111 with internet access run

```auto
cd ~
mkdir ~/src
git clone https://github/com/mazinlab/mkidgen3.git ~/src/
cd ~/src/mkidgen3
git checkout develop 
source /etc/profile.d/pynq_venv.sh
sudo pip3 install fpbinary pyserial
sudo pip3 install -e ~/src/mkidgen3

```

The HLS source code for the dac\_table IP is online [here](https://github.com/MazinLab/dac-replay/tree/master/src).

Bitstream + hwh + test notebook is attached for each board.  
[zcu111\_test.zip](https://discuss.pynq.io/uploads/short-url/bGaSLl6e8RSAvACeoPq0SdKpSl9.zip) (6.1 MB)  
[rfsoc4x2\_test.zip](https://discuss.pynq.io/uploads/short-url/5dIVve2frtXFiLsk2UotVtnrSD8.zip) (5.8 MB)

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [September 27, 2022, 7:55am UTC](https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702/2 "2022-09-27T07:55:22Z")

</div>

Hi Jenny,

Please see this post.

> [@Pynq 2.7 HLS registers write-only?](https://discuss.pynq.io/t/pynq-2-7-hls-registers-write-only/3668/5):
>
> Hi @baileyji, I am to blame for these changes, we’ve seen some cases where the board hangs because the register map tries to read from a “write-only” register. In your case Vivado is exporting these registers with the “write-only” access type and therefore pynq 2.7 will not read them. While we investigate a better way you can use the previous version of the registers.py file. Run this command in a Jupyter Lab terminal, and then restart any Jupyer Notebook you may have wget https://raw.github…

Preventing read access to write-only register is a choice we made. Because, some times some IP will not return a value when doing this and it will hang the board. If you are sure this register can be read, even if it is a write-only. You could modify the hwh file to reflect this, or revert to the way we did this in 2.6 as indicated in the post above.

Additionally, you can change the access mode if you are creating your own driver for this IP.

I am not sure why the difference between the two boards.

Mario

---

<div class="post-metadata">

**Author:** ![JennySmith888](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jennysmith888/32/1966_2.png) [@JennySmith888](https://discuss.pynq.io/u/JennySmith888)\
**Post date:** [September 27, 2022, 6:56pm UTC](https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702/3 "2022-09-27T18:56:28Z")

</div>

Ah I see what happened. My colleague (@baileyji ) made this patch on the ZCU111 and I guess we both forgot hah. The two register.py files on the boards are indeed different versions which explains the difference in behavior I’m seeing. Thanks Mario!

---

<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [September 27, 2022, 7:39pm UTC](https://discuss.pynq.io/t/rfsoc4x2-register-map-different-format/4702/4 "2022-09-27T19:39:41Z")

</div>

Closed on September 27, 2022, 7:39pm UTC