# RTL IP in PYNQ **URL:** \ **Category:** Support\ **Created:** [July 21, 2023, 8:52pm UTC](https://discuss.pynq.io/t/rtl-ip-in-pynq/5859 "2023-07-21T20:52:07Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![PAI](https://avatars.discourse-cdn.com/v4/letter/p/a87d85/32.png) [@PAI](https://discuss.pynq.io/u/PAI)\ **Post date:** [July 21, 2023, 8:52pm UTC](https://discuss.pynq.io/t/rtl-ip-in-pynq/5859/1 "2023-07-21T20:52:07Z")
![3](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/4/429958105c999ac833b18130df3696d49d582cdf.png) ## My block diagram includes RTL IP. That ip also consists of VHDL components and IP. I generate bit and hwh file. However, I got an error as follow: overlay=Overlay(“/home/xilinx/jupyter\_notebooks/Master/design. Bit”) error: CacheMetadataError Traceback (most recent call last) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:252, in BitstreamHandler.get\_parser(self, partial) 251 try: → 252 parser = self.\_get\_cache() 253 except CacheMetadataError: File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:228, in BitstreamHandler.\_get\_cache(self) 227 else: → 228 raise CacheMetadataError(f"No cached metadata present") CacheMetadataError: No cached metadata present During handling of the above exception, another exception occurred: WrongPolarityConnection Traceback (most recent call last) Input In [1], in \() 4 #from pynq.overlays.base import BaseOverlay 5 import pynq.lib.dma ----\> 6 overlay=Overlay(“/home/xilinx/jupyter\_notebooks/Master/design.bit”) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay. **init** (self, bitfile\_name, dtbo, download, ignore\_version, device, gen\_cache) 315 super(). **init** (bitfile\_name, dtbo, partial=False, device=device) 317 self.\_register\_drivers() → 319 self.device.set\_bitfile\_name(self.bitfile\_name) 320 self.parser = self.device.parser 322 self.ip\_dict = ( 323 self.gpio\_dict 324 ) = ( 325 self.interrupt\_controllers 326 ) = self.interrupt\_pins = self.hierarchy\_dict = dict() File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/device.py:118, in Device.set\_bitfile\_name(self, bitfile\_name) 116 def set\_bitfile\_name(self, bitfile\_name: str) → None: 117 self.bitfile\_name = bitfile\_name → 118 self.parser = self.get\_bitfile\_metadata(self.bitfile\_name) 119 self.mem\_dict = self.parser.mem\_dict 120 self.ip\_dict = self.parser.ip\_dict File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:690, in EmbeddedDevice.get\_bitfile\_metadata(self, bitfile\_name, partial) 689 def get\_bitfile\_metadata(self, bitfile\_name:str, partial:bool=False): → 690 parser = \_get\_bitstream\_handler(bitfile\_name).get\_parser(partial=partial) 691 if parser is None: 692 raise RuntimeError(“Unable to find metadata for bitstream”) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl\_server/embedded\_device.py:254, in BitstreamHandler.get\_parser(self, partial) 252 parser = self.\_get\_cache() 253 except CacheMetadataError: → 254 parser = RuntimeMetadataParser(Metadata(input=self.\_filepath.with\_suffix(“.hwh”))) 255 except: 256 raise RuntimeError(f"Unable to parse metadata") File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:40, in Metadata(input) 38 if os.path.isfile(input): 39 if str(input).endswith(“.hwh”): —\> 40 return HwhFrontend(\_hwhfile=input) 41 elif str(input).endswith(“.xsa”): 42 return XsaFrontend(input=input) File :25, in **init** (self, name, type, generic\_type, \_parent, \_children, ref, ext, \_timestamp, hierarchy\_name, ports, parameters, blocks, modules, busses, \_hierarchies, \_hwhfile, \_element\_tree, \_root, \_logical2physical\_portmap, \_physical2logical\_portmap, \_logical2physical\_extern\_pm, \_physical2logical\_extern\_pm) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:219, in HwhFrontend. **post\_init** (self) 207 “”" 208 Performs the parsing of the hwh into the metadata model 209 \* checks to see if the hwhfile is an XML string or a (…) 216 \* Performs a connectivity pass 217 “”" 218 if self.\_hwhfile != “”: → 219 self.parse() File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:241, in HwhFrontend.parse(self) 238 self.\_create\_external\_ports() 240 self.resolve\_addressing() → 241 self.connect\_signals() 243 self.refresh() File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh\_frontend.py:662, in HwhFrontend.connect\_signals(self) 657 dst\_signal = dst\_core.lookup( 658 f"{c\_dst}[port]:{c\_dst}[signal]" 659 ) 661 if isinstance(signal, Signal) and isinstance(dst\_signal, Signal): → 662 signal.connect(dst\_signal) 663 else: 664 raise ExpectedSignalType( 665 f"{signal} and {dst\_signal} were both expected to be of type Signal so that they could be connected" 666 ) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/signal.py:122, in Signal.connect(self, sig) 118 “”" 119 Connect this signal to sig 120 “”" 121 if not self.connection\_exists(sig): → 122 self.\_check\_polarity(sig) 123 self.\_connections[sig.ref] = sig 124 self.con\_refs.append(sig.ref) File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/signal.py:108, in Signal.\_check\_polarity(self, sig) 106 if not (self.external or sig.external): 107 if sig.driver == self.driver: → 108 raise WrongPolarityConnection( 109 f"{sig.ref} cannot be connected to {self.ref} as they have the same polarity (and are not external)" 110 ) 111 else: 112 if sig.driver != self.driver: WrongPolarityConnection: design\_1:axi\_interconnect\_0[block]:M02\_AXI[port]:AWPROT[signal] cannot be connected to design\_1:Master\_proj\_top\_0[block]:M02\_AXI\_0[port]:AWPROT[signal] as they have the same polarity (and are not external) Could you please let me know if PYNQ is compatible with creating a block diagram like my one? How can I solve the error? ---
**Author:** ![stf](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/stf/32/2724_2.png) [@stf](https://discuss.pynq.io/u/stf)\ **Post date:** [July 22, 2023, 5:39pm UTC](https://discuss.pynq.io/t/rtl-ip-in-pynq/5859/2 "2023-07-22T17:39:46Z")
Hi @PAI, welcome to the community! Can you share the .hwh file for your design so I can test it/debug it? All the best, Shane ---
**Author:** ![PAI](https://avatars.discourse-cdn.com/v4/letter/p/a87d85/32.png) [@PAI](https://discuss.pynq.io/u/PAI)\ **Post date:** [July 24, 2023, 3:15pm UTC](https://discuss.pynq.io/t/rtl-ip-in-pynq/5859/3 "2023-07-24T15:15:51Z")
Hi, how do you want to debug it? ---
**Author:** ![stf](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/stf/32/2724_2.png) [@stf](https://discuss.pynq.io/u/stf)\ **Post date:** [July 24, 2023, 4:23pm UTC](https://discuss.pynq.io/t/rtl-ip-in-pynq/5859/4 "2023-07-24T16:23:21Z")
In the same folder where you have the `design.bit` file do you have a file `design.hwh` file? Would you be able to share that .hwh file? All the best, Shane