# Run time error : DMA channel not idle **URL:** \ **Category:** Support\ **Created:** [May 25, 2021, 7:52pm UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699 "2021-05-25T19:52:03Z")\ **Posts on this page:** 11\ **Page:** 1
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 25, 2021, 7:52pm UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/1 "2021-05-25T19:52:03Z")
Hello everyone, I got this error while runing my code, I’m new to this and I don’t really understand where is the error or what does this error means, , Thank you! ![jkhkjh](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c9f1424ee7709b24bf35d0a1bf061b85fdb362f8.png) ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 26, 2021, 8:18am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/2 "2021-05-26T08:18:55Z")
The error is telling you the DMA is not idle, so the transfer() can’t start. Do you get the error the first time you run this code, or do you get it after you run this code multiple times? I see you are at [76] cells that have been run. Can you share the whole notebook, details of the hardware design, and board you are using, PYNQ version and any other relevant details? Cathal ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 26, 2021, 8:26am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/3 "2021-05-26T08:26:20Z")
Hello Cathal, Thank you for replying me, You’ll find attached the whole notebook, screenshots of the block design on Vivado, also I’m using the Ultra96 v2 board [PFE-maj-Copy1.ipynb](https://discuss.pynq.io/uploads/short-url/29fxS9lg6D6QyHwL7lFH0pCtFi1.ipynb) (622.6 KB) Farah ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 26, 2021, 8:27am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/4 "2021-05-26T08:27:03Z")
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**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 26, 2021, 8:27am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/5 "2021-05-26T08:27:40Z")
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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 26, 2021, 7:20pm UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/6 "2021-05-26T19:20:53Z")
Your config port for the FFT block is unconnected. Your notebook doesn’t seem to be running on the board - I see an error that it can’t find pynq. Can you make a really simple notebook with the code to test the DMA only and check that? Cathal Cathal ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 27, 2021, 7:38am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/7 "2021-05-27T07:38:38Z")
Should I connect it to the m\_axi\_mm2s\_aclk and m\_axi\_s2mm\_aclk or to the s\_axi\_lite\_aclk? And yes I was not running on board because I don’t have it in my hands but I will test it and post the result as possible. Thank you for your respond Farah ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 27, 2021, 7:54am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/8 "2021-05-27T07:54:43Z")
Even though it looks like they have different names inside the hierarchy, I think all your clocks are connected to ps\_clk0 so I think this is fine. Let me know if I did not understand your question. Cathal ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 27, 2021, 7:59am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/9 "2021-05-27T07:59:43Z")
Yes right all the clocks are connected to ps\_clk0, I connected now thes\_axis\_config\_data to the ps\_clk0 and the design is validated, is it right? Farah ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 27, 2021, 10:43am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/10 "2021-05-27T10:43:55Z")
I’ve tried with a test code (attached and I got the same error) [test1.ipynb](https://discuss.pynq.io/uploads/short-url/uRfbHc5chIIiAOxrdN2bPxQ4Muh.ipynb) (2.8 KB) ---
**Author:** ![farahbenrayana](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@farahbenrayana](https://discuss.pynq.io/u/farahbenrayana)\ **Post date:** [May 27, 2021, 10:44am UTC](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/11 "2021-05-27T10:44:41Z")
![dma](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/9/929a05159c5a23e1e4ef068c8c7f9fabe2f93997.png)