# RuntimeError: DMA channel not idle **URL:** \ **Category:** Support\ **Created:** [September 17, 2021, 6:19am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037 "2021-09-17T06:19:30Z")\ **Posts on this page:** 8\ **Page:** 1
**Author:** ![alavala\_suraj](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/alavala_suraj/32/2371_2.png) [@alavala\_suraj](https://discuss.pynq.io/u/alavala_suraj)\ **Post date:** [September 17, 2021, 6:19am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/1 "2021-09-17T06:19:30Z")
Hello, I have had this error when I am trying to learn how to use transfer to and fro from DRAM via AXI-DMA. I am attaching my Jupyter notebook code and block diagram. I am using avnet ultra-96 v2 board. I have gone through the solution mentioned in > [@Run time error : DMA channel not idle](https://discuss.pynq.io/t/run-time-error-dma-channel-not-idle/2699/2): > > The error is telling you the DMA is not idle, so the transfer() can’t start. Do you get the error the first time you run this code, or do you get it after you run this code multiple times? I see you are at [76] cells that have been run. Can you share the whole notebook, details of the hardware design, and board you are using, PYNQ version and any other relevant details? Cathal But could’ nt get it done.! ![block_diagram](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/b/baea707b5e2a1bb837d0cb6f59eeea2006669071.png) ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [September 17, 2021, 10:57am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/2 "2021-09-17T10:57:03Z")
Hi, I suggest you use an AXI4-Stream Data FIFO. The tlast signal of the mm2s channel is not being used and this can be causing an error. You can use this tutorial as a guideline > Mario ---
**Author:** ![alavala\_suraj](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/alavala_suraj/32/2371_2.png) [@alavala\_suraj](https://discuss.pynq.io/u/alavala_suraj)\ **Post date:** [September 18, 2021, 9:47am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/3 "2021-09-18T09:47:23Z")
Thanks Marioruiz, I will try this solution and get back to you. ---
**Author:** ![alavala\_suraj](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/alavala_suraj/32/2371_2.png) [@alavala\_suraj](https://discuss.pynq.io/u/alavala_suraj)\ **Post date:** [September 22, 2021, 6:55am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/4 "2021-09-22T06:55:11Z")
Hello Marioruiz, I have corrected the mistake you have pointed out. I have created a tlast signal as shown in the diagram. After that, when I tried sending the data, My kernel ran for a long time but I couldn’t get any output. I have attached my modified block diagram. ![Screenshot from 2021-09-22 12-24-26](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/d/d1e56416ec9eed11a6a0121eab6ff3f1ed8c2f3c.png) ---
**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\ **Post date:** [September 22, 2021, 8:05am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/5 "2021-09-22T08:05:43Z")
I suggest you use an AXI4-Stream Data FIFO. The DMA also uses the keep signal. And this is missing in your design. ---
**Author:** ![abdyoyo](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/abdyoyo/32/2297_2.png) [@abdyoyo](https://discuss.pynq.io/u/abdyoyo)\ **Post date:** [June 2, 2023, 9:05am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/6 "2023-06-02T09:05:17Z")
Where is the keep signal in the AXI4-Stream Data FIFO. I could not find it in the disabled ports as well when I opened the DMA IP. ---
**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\ **Post date:** [June 2, 2023, 9:20am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/7 "2023-06-02T09:20:48Z")
@abdyoyo From what i understand keep is only used when unaligned transfer. If aligned TRX no reason to use keep signal. ENJOY~ ---
**Author:** ![abdyoyo](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/abdyoyo/32/2297_2.png) [@abdyoyo](https://discuss.pynq.io/u/abdyoyo)\ **Post date:** [June 2, 2023, 9:31am UTC](https://discuss.pynq.io/t/runtimeerror-dma-channel-not-idle/3037/8 "2023-06-02T09:31:27Z")
Thanks Brian. The TRX is aligned as we are getting the data in frames perfectly.