# RuntimeError:"DMA does not support unaligned transfers"

**URL:** <https://discuss.pynq.io/t/runtimeerror-dma-does-not-support-unaligned-transfers/4977>\
**Category:** Support\
**Created:** [November 30, 2022, 12:03pm UTC](https://discuss.pynq.io/t/runtimeerror-dma-does-not-support-unaligned-transfers/4977 "2022-11-30T12:03:19Z")\
**Posts on this page:** 1\
**Showing post:** 8

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**Author:** ![briansune](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/briansune/32/3087_2.png) [@briansune](https://discuss.pynq.io/u/briansune)\
**Post date:** [November 30, 2022, 3:26pm UTC](https://discuss.pynq.io/t/runtimeerror-dma-does-not-support-unaligned-transfers/4977/8 "2022-11-30T15:26:34Z")

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@nirsap

Now this has become very confused:  
Chipscope or System-ILA?  
Why two DMAs signals are not aligned with the image you had post from beginning?  
Transaction ended successfully aka signals are what states?

Let’s wait @cathalmccabe answer. They are better on these questions.

But I will highly suggest u look from most common FIR DMA example:

> [@ZYNQ Ultrascale+ FIR DMA](https://discuss.pynq.io/t/zynq-ultrascale-fir-dma/4414):
>
> Hello all, After the MNIST on ZYNQ example, it is time to move to a better and more powerful platform ZYNQ Ultrascale (ARM is more powerful). This FIR example is based on the previous example [here](https://www.fpgadeveloper.com/2018/03/how-to-accelerate-a-python-function-with-pynq.html/). Although this is preformed on ZYNQ rather than ZYNQ-Ultrascale+, both platforms are so similar. In this example we are going to compare both software Python signal filter and HW accelerated filter. Lets start with the overall block-diagram. [fir\_acc.pdf](https://discuss.pynq.io/uploads/short-url/mDOUAokFEFJvifbfJtCNqXsTQWC.pdf) (385.5 KB) Take a closer lo…

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