# Server Connection Error - File Save Error design.ipynb **URL:** \ **Category:** Support\ **Created:** [May 13, 2024, 8:18pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004 "2024-05-13T20:18:42Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 13, 2024, 8:18pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/1 "2024-05-13T20:18:42Z")
**May 2024 -** PYNQ Version **Board -** RFSoC 4x2 **Issue -** I’ve built a Hardware Design where Programmable Logic can interface with DAC Channels on board the RFSoC 4x2 using Direct Memory Access. DMA is used to push symbols from PL DDR4 memory to the DAC path. I plan to view this on my oscilloscope as we are interested to observe processor emulation data on scope in future using this procedure. But, I have been facing error interfacing the DMA script from Base Overlay. The Jupyter Lab Server Connection keeps dropping off as it reattempts to connect but finally, it shows me “File Save Error for xxxx.ipynb” - failed to fetch. Surprisingly, for an older design that I worked on earlier it interfaces properly without dropping but for new designs it shows this problem. Facing this problem since past week, I’ve tried all sort of tricks and techniques but none have worked so far. Please help as soon as possible! ![Server Connection Error_When Calling DMA IP](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/7/7d678764cb1cb7bcd48004f87d6a1cb46004acd1.jpeg) ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/afc289db383f8c555bf0827228deb9a7ed6c89de.png) ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 13, 2024, 9:32pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/2 "2024-05-13T21:32:08Z")
Do you have to reset the board after the notebook hangs? If so, can you try split up the cell and execute the code line by line to check if this happens at a particular point in your code? You can hang the board if you access an invalid address. If this is happening, I’d suggest you check if your HWH is up-to-date with your .bit file. After that I would debug the hardware design (simulation first) to check it is working as expected. Cathal ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 13, 2024, 9:38pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/3 "2024-05-13T21:38:20Z")
Hey Cathal, Thank you for your response! This happens when I start to leverage DMA script to access the same from my hardware design. My Hardware works properly with simulation and bitstream generation is error and CW free. ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 13, 2024, 9:51pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/4 "2024-05-13T21:51:44Z")
Which line causes it to hang? Did you check your HWH and BIT files? Cathal ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 13, 2024, 10:01pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/5 "2024-05-13T22:01:35Z")
It’s basically the overlay.axi\_dma\_0, last line in the picture. ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/feca504b53c4762467a35360eb1192bbbe4f5b7f.png) How do I find discrepancy in .bit and .hwh files? Can you help me out, both files belong to the same project and is up-to-date if you mean by that. ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 14, 2024, 4:37pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/6 "2024-05-14T16:37:09Z")
> [@Sagar\_Sajeev](#): > > Can you help me out, both files belong to the same project and is up-to-date if you mean by that. Yes, this is what I mean. > [@Sagar\_Sajeev](#): > > gmat = rl.axi\_dma\_0 This is just variable assignment in software only - there is no interaction with the PL. I don’t know why this would cause your board to hang. I’d suggest trying a different SD card to make sure there isn’t a problem with the one you are using. Cathal ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 15, 2024, 6:46pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/7 "2024-05-15T18:46:39Z")
Sure Cathal, I’ll give it a shot. ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 15, 2024, 7:03pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/8 "2024-05-15T19:03:30Z")
Hey @cathalmccabe , on an other note, could it be some Jupyter configuration issue? I know that there some 100 mb cap on data accessed/transfered through Jupyter Notebook but my design is having .bit file worth 33 MB plus the hwh file of 387 KB which is well below the limit. ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 15, 2024, 9:04pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/9 "2024-05-15T21:04:03Z")
I’m not aware of such a limit, so I don’t think this is the issue. Cathal ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 15, 2024, 11:12pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/10 "2024-05-15T23:12:07Z")
I tried the same design on new SD Card with v3.0.1 PYNQ on RFSoC 4x2, it yields in the same Jupyter Server Connection Error. But, it does pass all the self tests etc. Very strange. ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/5/5fdeda9b3edf8d9632c9d81de8805c1b61fe4008.png) ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [May 16, 2024, 7:34am UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/11 "2024-05-16T07:34:38Z")
Hi, Can you share the BIT, HWH, IPYNB files? Cathal ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 17, 2024, 7:05pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/12 "2024-05-17T19:05:11Z")
Sure, Cathal. Sending it across shortly! ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 17, 2024, 7:31pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/14 "2024-05-17T19:31:28Z")
Here’s a compressed file - [DMA-DAC\_Design.zip](https://discuss.pynq.io/uploads/short-url/8PgztP508Jh77d9meaRC1Ytr0gY.zip) (600.8 KB) ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 22, 2024, 9:40pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/15 "2024-05-22T21:40:42Z")
Hello @cathalmccabe, any update from your tests? Is the design properly running on your end? ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [May 31, 2024, 9:58pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/16 "2024-05-31T21:58:06Z")
Hello @cathalmccabe, any update from your tests? Is the design properly running on your end? ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [June 11, 2024, 11:36pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/17 "2024-06-11T23:36:03Z")
Hello @cathalmccabe, any update from your tests? Is the design properly running on your end? ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 12, 2024, 6:19pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/18 "2024-06-12T18:19:20Z")
Did you add blocks from the base Overlay in your custom Overlay? If so, could you try the help function, to be sure that the new overlay is correctly read by the board? For a project I am trying to add a DMA block to the transmitter part. I generated the bitstream and imported the .bit, .hwh and .tcl to my board. I placed them in a folder in the same location as the base Overlay provided by AMD. And when I do a help function, the RFSoC 4x2 is recognizing my new block, via help(overlay.radio.transmitter.axi\_dma) ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [June 12, 2024, 11:56pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/19 "2024-06-12T23:56:44Z")
Hi Matthew, Do I have to copy the whole structure in a directory to base? ---
**Author:** ![Sagar\_Sajeev](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/sagar_sajeev/32/5833_2.png) [@Sagar\_Sajeev](https://discuss.pynq.io/u/Sagar_Sajeev)\ **Post date:** [June 13, 2024, 12:18am UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/20 "2024-06-13T00:18:04Z")
![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/2dcdd62da09a02ef09a5048030dd6e5f9ee416d6.png) It’s the same error plus I don’t require the Base Overlay unless there is some functionality to write to DAC directly. Nevertheless, the help command crashes too ---
**Author:** ![matthew](https://avatars.discourse-cdn.com/v4/letter/m/ed655f/32.png) [@matthew](https://discuss.pynq.io/u/matthew)\ **Post date:** [June 13, 2024, 2:12pm UTC](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004/21 "2024-06-13T14:12:30Z")
In your board, check the folder “overlays” in /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlays/ . There should be a folder “base” with the base.bit and base.hwh inside. If there is that folder, go back to Overlays and create a folder with the name of your bitstream. In that folder put the .bit, .tcl and .hwh generated when you generated the bitstreeam. All should have the same name. Then retry your code. You can later remove that folder if it did not work. [edit] the .tcl is not needed. The required files are the .bit and .hwh to use the command “Overlay”. But to use “BaseOverlay”, a python class is required like base.py and the other files in the folder “base” [Next page](https://discuss.pynq.io/t/server-connection-error-file-save-error-design-ipynb/7004.md?page=2)