# Stuck at dma.recvchannel.wait() in DMA → DAC → ADC → DMA Loop

**URL:** <https://discuss.pynq.io/t/stuck-at-dma-recvchannel-wait-in-dma-dac-adc-dma-loop/8450>\
**Category:** Support\
**Created:** [May 22, 2025, 7:26am UTC](https://discuss.pynq.io/t/stuck-at-dma-recvchannel-wait-in-dma-dac-adc-dma-loop/8450 "2025-05-22T07:26:21Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![StevenG](https://avatars.discourse-cdn.com/v4/letter/s/6de8d8/32.png) [@StevenG](https://discuss.pynq.io/u/StevenG)\
**Post date:** [May 22, 2025, 7:26am UTC](https://discuss.pynq.io/t/stuck-at-dma-recvchannel-wait-in-dma-dac-adc-dma-loop/8450/1 "2025-05-22T07:26:21Z")

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Hi everyone,

I’m currently trying to implement a simple **DMA → DAC → ADC → DMA loopback** on my ZCU111 board using PYNQ. My goal is to send a waveform from the PS via DMA to the DAC, loop it back to the ADC through the analog path, and then retrieve the sampled data back into DDR using the DMA receive channel.

My **Block Design** and configuration details are provided as follows:

block design  
[system.pdf](https://discuss.pynq.io/uploads/short-url/9iKmgkS4VbkL0O8YTF55fyfZ4I5.pdf) (117.2 KB)

 ![7931747898511_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/ec087d3d790ba17c1f322cc2f1b762b0bac875a0.png)

Settings:

 ![7751747898191_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/a1ddab1e03f33c5972c9952f9a2cdf5636e4ebba.png)  
 ![7761747898211_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3c606df963e71a06352f4c3d4a4994f510eb4b81.png)  
 ![7811747898280_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/89f1cbac0aaf55610f4c16cbcd9cadfcc2cc937e.png)  
 ![7771747898229_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/a/ad684266056b1615adaa0b9693b92152705f8819.png)  
 ![7781747898240_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/5/52560f587921a16f87ae52cd9755753919937037.png)  
 ![7791747898253_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3316132b36db0422ee26aca2805b627a94ac6d62.png)  
 ![7801747898268_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/05cca0ddc870cbe7e857d1c7e08ba7c8ed89617a.png)  
 ![7811747898280_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/8/89f1cbac0aaf55610f4c16cbcd9cadfcc2cc937e.png)

PYNQ Code:

 ![7821747898374_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/9/96479ee8f779515d297eaa21500835dada43580d.png)  
 ![7831747898391_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/e/e22bb8e6b8a475049570750412a14abe05f48f5d.png)  
 ![7841747898402_.pic](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/c/c072b1bb7980641e32209d20dbf5d302b92070b6.png)

However, I’m currently stuck at the following line in my Python code:

```auto
dma.recvchannel.wait() # program hangs here

```

The program hangs at `wait()`, and no data is ever received.

* * *

### Suspected Issues:

1. **TLAST not being generated** on the ADC → DMA (S2MM) path, causing the DMA to never detect end-of-frame.
2. **The RF-ADC might not be outputting any data** , due to incorrect configuration (e.g., Mixer, Decimation, Tile Clock, etc.).
3. If the number of samples I want to transfer is large e.g., 2048, it will get stuck at dma.sendchannel.wait(). If the number is small, e.g. 256, it will get stuck at dma.recvchannel.wait().

* * *

Could someone please help me identify what might be wrong? Are there any **critical settings** in the RFDC IP or Tile Clocking tab or Subset Converter that I might have misconfigured?

Any suggestions or advice are greatly appreciated.

Thank you in advance!

Best regards,  
Steven

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [May 22, 2025, 9:32am UTC](https://discuss.pynq.io/t/stuck-at-dma-recvchannel-wait-in-dma-dac-adc-dma-loop/8450/2 "2025-05-22T09:32:05Z")

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Hi @StevenG,

Welcome to the PYNQ community.

I wrote a series of blogs to add ILA in the design to debug this type of issues.  
I would suggest you add ILAs at different points in the data path and check if data is flowing.

> [@Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) \[Part 1\]](https://discuss.pynq.io/t/designing-an-overlay-using-vivado-integrated-logic-analyzer-ila-part-1/7155):
>
> Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) In this series of blogs, I will cover how to use the Integrated Logic Analyzer (ILA) to debug your overlay. Instrumenting an ILA should be your last resort when it comes down to debugging. Simulation and co-simulation are the best way to verify your design, although debugging in the actual hardware can be very useful. The main reason for these series of blogs is to address some of the most common issues that are reported in the …

Mario