# Stuck at recvchannel.wait()

**URL:** <https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640>\
**Category:** Support\
**Created:** [May 11, 2021, 8:33am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640 "2021-05-11T08:33:06Z")\
**Posts on this page:** 8\
**Page:** 1

<div class="post-metadata">

**Author:** ![sunwy](https://avatars.discourse-cdn.com/v4/letter/s/8797f3/32.png) [@sunwy](https://discuss.pynq.io/u/sunwy)\
**Post date:** [May 11, 2021, 8:33am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/1 "2021-05-11T08:33:06Z")

</div>

I am using Ultra96v2, and tried my own HLS IP. But the code in jupyer notebook always stuck at recvchannel.wait(). How to deal with this?

Here is my Block design, the HLS IP is called HLS\_accel\_0.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/1bab2e0e5cf717a5f137e274f117026ceda54b33.png)

The hls code is atteched below, and the main inferface function is defined as

```auto
void Hls_accel(hls::stream<AXI_DMA_IO> &stream_in, hls::stream<AXI_DMA_IO> &stream_out,
		int a, int b, int &c){
#pragma HLS INTERFACE s_axilite register port=return
#pragma HLS INTERFACE s_axilite port=b
#pragma HLS INTERFACE s_axilite port=a
#pragma HLS INTERFACE s_axilite port=c
#pragma HLS INTERFACE axis register both port=stream_in
#pragma HLS INTERFACE axis register both port=stream_out

c = a + b;

#pragma HLS DATAFLOW
stream<ap_uint<IN0_CH*ACT_BW_D> > img_in("img_in_stream");
strm_image<IN0_ROW,IN0_COL,IN0_CH,ACT_BW_D>(stream_in, img_in);
strm_out<IN0_ROW, IN0_COL, IN0_CH, ACT_BW_D>(img_in, stream_out);
}

```

AXI\_DMA\_IO is defined in main.h.

```auto
struct AXI_DMA_IO{
        ap_uint<64> data;
        ap_uint<1> last;
};

```

strm\_image and strm\_out is defined in function.h

```auto
template <	unsigned IN_ROW,
			unsigned IN_COL,
			unsigned IN_CH,
			unsigned BW
		>
void strm_image(hls::stream<AXI_DMA_IO> &stream_in, hls::stream<ap_uint<IN_CH*BW> > &in){
	AXI_DMA_IO tmp;
//	static_assert(sizeof(tmp.data)==sizeof(ap_int<IN_CH*BW>),"DMA width != img_in width");
	for (int i = 0; i < IN_ROW*IN_COL; i++){
#pragma HLS PIPELINE
		tmp = stream_in.read();
		in.write(tmp.data);
	}
}

template <	unsigned IN_ROW,
			unsigned IN_COL,
			unsigned IN_CH,
			unsigned BW
		>
void strm_out(hls::stream<ap_uint<IN_CH*BW> > & img_out, hls::stream<AXI_DMA_IO>& stream_out){
	AXI_DMA_IO tmp;
//	static_assert(sizeof(tmp.data)==sizeof(ap_int<IN_CH*BW>),"DMA width != img_in width");
	for (int i = 0; i < IN_ROW*IN_COL; i++){
#pragma HLS PIPELINE
		tmp.data = img_out.read();
		if(i == IN_ROW*IN_COL -1)
			tmp.last = 1;
		else
			tmp.last = 0;
		stream_out.write(tmp);
	}

}

```

[hls\_code.zip](https://discuss.pynq.io/uploads/short-url/ecQDIEEhsQLyUYttXtm5j41Qowl.zip) (2.4 KB)

The jupyer code is

```auto
from pynq import Overlay
import pynq
import numpy as np
overlay = Overlay('./design_1.bit')
dma_x = overlay.axi_dma_0.sendchannel
dma_y = overlay.axi_dma_0.recvchannel
x = np.random.randint(0, 10, size=(4,4), dtype=np.uint64)
buff_x = pynq.allocate(shape=(4,4), dtype=np.int64)
buff_x[:] = x
buff_y = pynq.allocate(shape=(4,4), dtype=np.uint64)
dma_x.transfer(buff_x)
dma_y.transfer(buff_y)
dma_x.wait()
dma_y.wait()

```

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<div class="post-metadata">

**Author:** ![sunwy](https://avatars.discourse-cdn.com/v4/letter/s/8797f3/32.png) [@sunwy](https://discuss.pynq.io/u/sunwy)\
**Post date:** [May 11, 2021, 8:39am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/2 "2021-05-11T08:39:03Z")

</div>

The program stuck at dma\_y.wait()  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/232e660bdd733a5c9d8ca14a95e37a67134d40cf.png)

My .bit/.tcl/.hwh files are attached below  
[bit\_hwh\_tcl.zip](https://discuss.pynq.io/uploads/short-url/pW4IazybV809YV1HeLTVhFz3LQO.zip) (261.3 KB)

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [May 11, 2021, 10:19am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/3 "2021-05-11T10:19:06Z")

</div>

Hi @sunwy,

Which pynq sdcard image version are you using?  
This may be related to this question

> [@Using AXI DMA on ZCU104](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779):
>
> I recently switch my works from PYNQ-Z2 to ZCU104. However, I get a problem on my first exercise, which is multiplying each elements in a given array by 3. I can receive the result, but it is incorrect. And any suggestion would be appreciated. My input is PynqBuffer([0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76], dtype=uint32) the expected output is multiplying each element by 3. However, the result I obtained is PynqBuffer([ 0, 0, 0, 0…

Mario

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<div class="post-metadata">

**Author:** ![sunwy](https://avatars.discourse-cdn.com/v4/letter/s/8797f3/32.png) [@sunwy](https://discuss.pynq.io/u/sunwy)\
**Post date:** [May 11, 2021, 11:06am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/4 "2021-05-11T11:06:38Z")

</div>

Hi, I‘m using ultra96v2\_v2.5. Do you have any suggestiongs? Thanks very much!

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<div class="post-metadata">

**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [May 11, 2021, 11:14am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/5 "2021-05-11T11:14:53Z")

</div>

Is the AXI HP0 FPD Data with set to 128? Like suggested here

> [@Using AXI DMA on ZCU104](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/5):
>
> Yes - they should be 128. There has to be a match between that setting and what’s configured in software when the board boots and the block design. For the PYNQ boot files we keep the default of 128 so that’s what the block design should have as well. Peter

I would also suggest to burn the 2.6 pynq image.

You may also want to check if the `stream_out` is asserting `tlast` by adding a ChipScope on your design.

Mario

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<div class="post-metadata">

**Author:** ![momo\_flyer](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/momo_flyer/32/874_2.png) [@momo\_flyer](https://discuss.pynq.io/u/momo_flyer)\
**Post date:** [May 11, 2021, 11:18am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/6 "2021-05-11T11:18:40Z")

</div>

You don’t seem to be starting your HLS IP.  
add to your jupyter code:  
hls\_ip=overlay.Hls\_accel\_0

and before your wait functions:  
hls\_ip.write(0x00,0x01) #this sets the ip\_start bit so the core starts processing the data

also, connect the DMA interrupts to your PS

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<div class="post-metadata">

**Author:** ![sunwy](https://avatars.discourse-cdn.com/v4/letter/s/8797f3/32.png) [@sunwy](https://discuss.pynq.io/u/sunwy)\
**Post date:** [May 12, 2021, 1:56am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/7 "2021-05-12T01:56:43Z")

</div>

Thanks for the suggestions, I will try 2.6 image later!

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<div class="post-metadata">

**Author:** ![sunwy](https://avatars.discourse-cdn.com/v4/letter/s/8797f3/32.png) [@sunwy](https://discuss.pynq.io/u/sunwy)\
**Post date:** [May 12, 2021, 1:57am UTC](https://discuss.pynq.io/t/stuck-at-recvchannel-wait/2640/8 "2021-05-12T01:57:35Z")

</div>

Yes, hls\_ip.write(0x00,0x01) really works. Thanks very much!