# The final steps to a feedthrough implementation?

**URL:** <https://discuss.pynq.io/t/the-final-steps-to-a-feedthrough-implementation/5848>\
**Category:** Support\
**Created:** [July 18, 2023, 6:08pm UTC](https://discuss.pynq.io/t/the-final-steps-to-a-feedthrough-implementation/5848 "2023-07-18T18:08:16Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![redson](https://avatars.discourse-cdn.com/v4/letter/r/cab0a1/32.png) [@redson](https://discuss.pynq.io/u/redson)\
**Post date:** [July 18, 2023, 6:08pm UTC](https://discuss.pynq.io/t/the-final-steps-to-a-feedthrough-implementation/5848/1 "2023-07-18T18:08:16Z")

</div>

PYNQ3.0.1, ZCU208

After crawling through documentation and making incremental changes, I’ve finally been able to fully initialize the RFDC IP Core with some stuff attached to it. Now, what I would like to do is to use it to feed data from a function generator into the ADC, and read it back out from the DAC. Eventually I would like to store the data in a streaming pipelined fashion through memory to simulate the effects of long signal delays from a transmitter to a receiver, but… baby steps first.

Here’s the block design. I cribbed the packet controller IP because I thought perhaps TLAST not existing out of the RFDC core (I don’t understand why there isn’t one??) was the problem. I write “1” to the S\_AXI registers required to enable the packet generator and pass in that the packet size is 1, so TLAST should go high on every transfer.  
[zcu208\_RF0.pdf](https://discuss.pynq.io/uploads/short-url/wXHy1TVGpN8kvbl16pAbkCZNEXf.pdf) (247.6 KB)  
The configuration of the RFDC IP is almost identical to that of the Radio example project.

First I would like to be able to read data into the memory from the ADC. I’ve dug around through some of the Base overlay and the radio receiver IP, and I think I’ve managed to configure my DMA correctly (since using that overlay I can read in accurate data no problem) but alas:  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/3608253d30d6535e8aa676e2a8a09db355beaec3.png)  
No data seems to get sent into the SoC environment, even though the Zynq PS DDR addresses are correctly assigned to the DMA M\_AXI networks. Eventually I think I need to use the Data Mover IP to stream send/receive commands to keep the data flowing through the fabric without pause, but for the time being I’d be satisfied with sampling a signal and regenerating it on the other side (perhaps with some DC offset and adjusted gain).

Not sure at the moment where to look next for something to fix – there’s smoke coming out of my ears already from digging around in registers all day. Any pointers would be greatly appreciated.

Cheers,  
Reid