# TLAST Issue
**URL:** https://discuss.pynq.io/t/tlast-issue/4321
**Category:** Support
**Created:** [June 7, 2022, 11:36am UTC](https://discuss.pynq.io/t/tlast-issue/4321 "2022-06-07T11:36:52Z")
**Posts on this page:** 9
**Page:** 1
### Author:  [@Nagendra](https://discuss.pynq.io/u/Nagendra)
#### Post date: [June 7, 2022, 11:36am UTC](https://discuss.pynq.io/t/tlast-issue/4321/1 "2022-06-07T11:36:53Z")
Hi everyone.
I am using Vivado 2019.2, vivado\_hls, PYNQ 2.7, and the ZCU111 board. is it fine to use vivado 2019.2 for PYNQ 2.7 or should i upgrade to the new version of Vivado to not face any internal version issues .
I have assigned TLAST in my HLS design. It has a 1 bit data width, but when it comes to ILA debugging, it shows zero.
**HLS summary**
**Vivado IP:**
**ILA Waveform**
I checked my IP with ILA. To complete the DMA transaction, the TLAST signal is set to zero; it should be the rising edge of the trigger. How I can set the TLAST for rising edge of the trigger? any suggestions ?
Thank You.
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### Author:  [@marioruiz](https://discuss.pynq.io/u/marioruiz)
#### Post date: [June 7, 2022, 12:24pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/2 "2022-06-07T12:24:45Z")
Are you asserting TLAST in your code?
The window in the ILA you are showing does not seems to be completed.
Mario
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### Author:  [@Nagendra](https://discuss.pynq.io/u/Nagendra)
#### Post date: [June 7, 2022, 4:41pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/3 "2022-06-07T16:41:35Z")
Yes,
I have assigned the TLAST in the HLS code. But in the ILA it shows zero, so how can I turn to the rising edge of the trigger?
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### Author:  [@marioruiz](https://discuss.pynq.io/u/marioruiz)
#### Post date: [June 7, 2022, 4:59pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/4 "2022-06-07T16:59:44Z")
You can watch this video to learn how to use the ILA.
[Logic Debug in Vivado](https://www.xilinx.com/video/hardware/logic-debug-in-vivado.html) controls
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### Author:  [@Nagendra](https://discuss.pynq.io/u/Nagendra)
#### Post date: [June 7, 2022, 5:29pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/5 "2022-06-07T17:29:00Z")
Do you mean my ILA debugging process is wrong?
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### Author:  [@marioruiz](https://discuss.pynq.io/u/marioruiz)
#### Post date: [June 7, 2022, 6:12pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/6 "2022-06-07T18:12:13Z")
No,
Towards the end the video cover your question: “so how can I turn to the rising edge of the trigger?”
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### Author:  [@Nagendra](https://discuss.pynq.io/u/Nagendra)
#### Post date: [June 8, 2022, 2:00pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/7 "2022-06-08T14:00:25Z")
Hi,
I have changed TLAST from 0 to 1 in the HLS, so the trigger edge is raised but the DMA transaction is not completing.
can you give any suggestions?
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### Author:  [@marioruiz](https://discuss.pynq.io/u/marioruiz)
#### Post date: [June 8, 2022, 2:08pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/8 "2022-06-08T14:08:14Z")
Hi @Nagendra,
These type of questions are outside of the scope of the PYNQ support.
I suggest you familiarize yourself with AXI4-Stream and how the DMA works. As you will learn from the link below, `TLAST` signals the last byte of the stream so it cannot be asserted all the time.
A good starting point here [How-AXI4-Stream-Works](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/How-AXI4-Stream-Works)
You can also review Cathal’s tutorial [Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344), you can add ILA in that design so you can learn how it is working.
Mario
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### Author:  [@Nagendra](https://discuss.pynq.io/u/Nagendra)
#### Post date: [June 8, 2022, 2:10pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/9 "2022-06-08T14:10:05Z")
Hi @marioruiz
Thank you for your suggestions