# TLAST Issue

**URL:** <https://discuss.pynq.io/t/tlast-issue/4321>\
**Category:** Support\
**Created:** [June 7, 2022, 11:36am UTC](https://discuss.pynq.io/t/tlast-issue/4321 "2022-06-07T11:36:52Z")\
**Posts on this page:** 1\
**Showing post:** 8

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [June 8, 2022, 2:08pm UTC](https://discuss.pynq.io/t/tlast-issue/4321/8 "2022-06-08T14:08:14Z")

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Hi @Nagendra,

These type of questions are outside of the scope of the PYNQ support.

I suggest you familiarize yourself with AXI4-Stream and how the DMA works. As you will learn from the link below, `TLAST` signals the last byte of the stream so it cannot be asserted all the time.

A good starting point here [How-AXI4-Stream-Works](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/How-AXI4-Stream-Works)

You can also review Cathal’s tutorial [Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)](https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344), you can add ILA in that design so you can learn how it is working.

Mario

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