# Tlast signal?

**URL:** <https://discuss.pynq.io/t/tlast-signal/6370>\
**Category:** Support\
**Created:** [November 27, 2023, 1:16pm UTC](https://discuss.pynq.io/t/tlast-signal/6370 "2023-11-27T13:16:57Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![shiqi17](https://avatars.discourse-cdn.com/v4/letter/s/e99b99/32.png) [@shiqi17](https://discuss.pynq.io/u/shiqi17)\
**Post date:** [November 27, 2023, 1:16pm UTC](https://discuss.pynq.io/t/tlast-signal/6370/1 "2023-11-27T13:16:57Z")

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Seeing a lot of articles mentioning the use of DMA to set up the TLAST signal, I use HLS to create the IP cores, connect in vivado. Where and where should the TLAST signal be set in which software?

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [November 27, 2023, 2:25pm UTC](https://discuss.pynq.io/t/tlast-signal/6370/2 "2023-11-27T14:25:48Z")

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Hi @shiqi17,

I would suggest you familiarize yourself with the AXI4 standard and in particular the stream version.

There are a few post in the forum that deals with this, for instance:

> [@TLAST Issue](https://discuss.pynq.io/t/tlast-issue/4321):
>
> Hi everyone. I am using Vivado 2019.2, vivado\_hls, PYNQ 2.7, and the ZCU111 board. is it fine to use vivado 2019.2 for PYNQ 2.7 or should i upgrade to the new version of Vivado to not face any internal version issues . I have assigned TLAST in my HLS design. It has a 1 bit data width, but when it comes to ILA debugging, it shows zero. HLS summary [Screenshot from 2022-06-07 19-15-05] Vivado IP: [Screenshot from 2022-06-07 19-34-38] ILA Waveform I checked my IP with ILA. To complete the D…

> [@TLAST signal not synthesized!](https://discuss.pynq.io/t/tlast-signal-not-synthesized/3420):
>
> Hello all, I’m using an axis interface for data in and out (eventually using DMA) but with floating point type. So i need to set the TLAST signal manually, as a million tutorials suggested. But in my case, it doesn’t get synthesized for some reason. Here is my code: void fit(hls::stream\<axis\_t\> &in, hls::stream\<axis\_t\> &out, float lambda, float gamma) { #pragma HLS INTERFACE axis port=in #pragma HLS INTERFACE axis port=out #pragma HLS INTERFACE s\_axilite port=lambda #pragma HLS INTERFACE s\_a…

Code example here: [https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Interface/Streaming](https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Interface/Streaming)

Mario

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<div class="post-metadata">

**Author:** ![shiqi17](https://avatars.discourse-cdn.com/v4/letter/s/e99b99/32.png) [@shiqi17](https://discuss.pynq.io/u/shiqi17)\
**Post date:** [November 28, 2023, 1:12am UTC](https://discuss.pynq.io/t/tlast-signal/6370/3 "2023-11-28T01:12:37Z")

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thank you！I will try.