# Tutorial: AXI Master interfaces with HLS IP

**URL:** <https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032>\
**Category:** Learn\
**Created:** [April 12, 2022, 8:20pm UTC](https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032 "2022-04-12T20:20:17Z")\
**Posts on this page:** 1\
**Showing post:** 4

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**Author:** ![haipnh](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/haipnh/32/4439_2.png) [@haipnh](https://discuss.pynq.io/u/haipnh)\
**Post date:** [April 20, 2022, 9:25am UTC](https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032/4 "2022-04-20T09:25:06Z")

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Thanks for your update. It ran successfully.

```auto
INFO: [SIM 2] ***************CSIM start***************
INFO: [SIM 4] CSIM will launch GCC as the compiler.
   Compiling ../../../../../src/example_test.cpp in debug mode
   Generating csim.exe
HLS AXI-Stream no side-channel data example
Success HW and SW results match
INFO: [SIM 1] CSim done with 0 errors.
INFO: [SIM 3] ***************CSIM finish***************

```

This is how the block design looks like on MPSoC platform. I tested on ZCU104.

 ![Screenshot from 2022-04-20 17-22-51](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/3/34d15233b5cd81e62ad4c6baa2a658b07054b49e.png)

Don’t forget setting the data width of S\_AXI\_HP0\_FPD to 32-bit.

 ![Screenshot from 2022-04-20 17-35-04](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/4/49452fd65a6dd9272dbc7f75120eb78333a039f0.png)

And the final results:

 ![Screenshot from 2022-04-20 17-23-59](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/fde7a65860baaa8da4f8624ce0b5421323f3a83d.png)

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