# Tutorial: Creating a new Verilog Module Overlay

**URL:** <https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530>\
**Category:** Learn\
**Created:** [July 19, 2020, 7:34pm UTC](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530 "2020-07-19T19:34:13Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [July 20, 2020, 9:02am UTC](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530/2 "2020-07-20T09:02:22Z")

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Great, thanks for sharing!

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_[View the full topic](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530)._