# Ultra96, Pynq Overlay, Enable PL HD\_GPIOs **URL:** \ **Category:** Support\ **Created:** [August 28, 2019, 7:21am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422 "2019-08-28T07:21:30Z")\ **Posts on this page:** 11\ **Page:** 1
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 28, 2019, 7:21am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/1 "2019-08-28T07:21:30Z")
Hello I am using the Ultra96 board with Pynq: (PYNQ Linux, based on Ubuntu 18.04 (GNU/Linux 4.14.0-xilinx-v2018.3 aarch64)) I just have a basic issue with the assignment of the PL HD\_GPIOs. First I need a hint where to find the default base.bit file. Then I need to know how to adapt it to assign the mentioned GPIOs 0-14 to be able to control them over Python. Have someone an example bit file? Thanks in advance. Roger ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 28, 2019, 9:46am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/2 "2019-08-28T09:46:20Z")
Hi Roger, You can find PYNQ docs related to the Ultra96 here: [Welcome to Ultra96-PYNQ’s documentation! — Ultra96-PYNQ v2.6 documentation](https://ultra96-pynq.readthedocs.io/en/latest/) If you want to change pin assignments, the project files for the base overlay are here: > **[Ultra96-PYNQ/Ultra96/sensors96b at master · Avnet/Ultra96-PYNQ](https://github.com/Avnet/Ultra96-PYNQ/tree/master/Ultra96/sensors96b)** > > master/Ultra96/sensors96b (This can be found from the previous link) Cathal ---
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 28, 2019, 10:57am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/3 "2019-08-28T10:57:27Z")
Thank you for your feedback. I checked the pages already, but I still need some add support. for example: - Can I adapt the .bit files on the pynq directly without vivado? (dont understand the doc in details) - If yes, where I have to add the GPIO Configuration? Regards Roger ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 28, 2019, 10:58am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/4 "2019-08-28T10:58:36Z")
What do you want to do with the board? You need to modify the design in Vivado if you want to change the design, but you may not need to do this. Cathal ---
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 28, 2019, 12:55pm UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/5 "2019-08-28T12:55:49Z")
I will have a simple Python programm running on the PS (pynq) part, which needs to control 14 GPIOs (as output (0/1)) which are on the PL side (HD\_gpio\_0 - 14). ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 28, 2019, 2:29pm UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/6 "2019-08-28T14:29:09Z")
If you want to build your own design, I suggest you install Vivado, and follow the instructions to rebuild the existing base design. You could try follow parts of this tutorial to add an AXI GPIO controller to connect to the pins you need: > [@Tutorial: Creating a hardware design for PYNQ](https://discuss.pynq.io/t/tutorial-creating-a-hardware-design-for-pynq/145): > > Creating a new hardware design for PYNQ The previous tutorial showed how to rebuild the reference base design for the PYNQ-Z1/PYNQ-Z2 boards. This tutorial will show you how to create a new Vivado hardware design for PYNQ. This tutorial is based on the v2.4 PYNQ image and will use Vivado 2018.2. The PYNQ-Z2 board was used to test this design. If you are using the PYNQ-Z1 or PYNQ-Z2, first make sure the board files have been installed. Download the [PYNQ-Z1 board files](https://github.com/cathalmccabe/pynq-z1_board_files/raw/master/pynq-z1.zip) or the [PYNQ-Z2 board files](https://dpoauwgwqsy2x.cloudfront.net/Download/pynq-z2.zip),… (You only need 1 AXI GPIO controller, and you don’t need the BRAM controller). Cathal ---
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 29, 2019, 1:06pm UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/7 "2019-08-29T13:06:12Z")
Thank you. Now the bit tcl and hwh files are done and in the pynq dir. Now I have to load the Overlay (design\_1.bit) file over the /pynq/overlay.py? ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 29, 2019, 2:26pm UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/8 "2019-08-29T14:26:11Z")
Yes, just add the path to your .bit when instantiating the overlay overlay = Overlay(“./path/to/my.bit”) [https://pynq.readthedocs.io/en/v2.4/pynq\_overlays/loading\_an\_overlay.html](https://pynq.readthedocs.io/en/v2.4/pynq_overlays/loading_an_overlay.html) Cathal ---
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 30, 2019, 9:38am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/9 "2019-08-30T09:38:44Z")
Hello So,now it worked so far. But I only see 1 axi\_gpio: ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/520148dd300c1030e37714dd5c0741cb446b6592.png) instead of 14.with the “overlay.ip\_dict.keys()” How can I see all listed? Wih kind regards Roger ---
**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\ **Post date:** [August 30, 2019, 9:42am UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/10 "2019-08-30T09:42:17Z")
You should only have one controller, connected to 14 pins. If you use the PYNQ AXI GPIO class, you could write 0x3fff, to set all the pins to 1. Some other material/examples here of AXI GPIO > Cathal ---
**Author:** ![roka](https://avatars.discourse-cdn.com/v4/letter/r/d78d45/32.png) [@roka](https://discuss.pynq.io/u/roka)\ **Post date:** [August 30, 2019, 12:55pm UTC](https://discuss.pynq.io/t/ultra96-pynq-overlay-enable-pl-hd-gpios/422/11 "2019-08-30T12:55:10Z")
It looks good. Have to adjust some Pins, will give you a feedback next week. Thanks a lot so far, was a great help! Regards Roger