# Understanding DMA's behavior

**URL:** https://discuss.pynq.io/t/understanding-dmas-behavior/1432
**Category:** Support
**Created:** [June 29, 2020, 6:02am UTC](https://discuss.pynq.io/t/understanding-dmas-behavior/1432 "2020-06-29T06:02:11Z")
**Posts on this page:** 1
**Page:** 1

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### Author: ![Kayzh3r](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/kayzh3r/32/884_2.png) [@Kayzh3r](https://discuss.pynq.io/u/Kayzh3r)
#### Post date: [June 29, 2020, 6:02am UTC](https://discuss.pynq.io/t/understanding-dmas-behavior/1432/1 "2020-06-29T06:02:11Z")

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Hi all,  
Recently I have been working on an introduction project with some IPs created in System Generator and HLS. The idea of the project-notebook was to understand the behavior of DMA.  
I found some troubles and some quite-strange behavior that I can not understand.  
Instead of creating a huge post, I preferred to create a repository with all necessary code and also a semi-explicative notebook.  
The URL of the notebook is [AXI\_interfaces/AXI\_interfaces.ipynb at master · Kayzh3r/AXI\_interfaces · GitHub](https://github.com/Kayzh3r/AXI_interfaces/blob/master/Notebooks/AXI_interfaces.ipynb)  
The idea is to focus on the hierarchies multiplier\_hls\_stream and multiplier\_stream. Both hierarchies do the same, multiplying an input AXI4 Stream of UInt32 to an AXILite Uint32. I have two main questions:

1. Why the limit of transfer buffer in **HLS Multiplier** is 1024 samples of Uint32? If I select more, I meant 2048, when I call _wait_ method the application hangs

2. Why the limit of transfer buffer in **Stream Multiplier** is 4 samples of Uint32? If I select more, I meant 5, when I call _wait_ method the application hangs having the DMA IP block configuration than **HLS Multiplier**

Thank so much, kind regards