# Using AXI DMA on ZCU104

**URL:** <https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779>\
**Category:** Support\
**Created:** [December 19, 2019, 5:53pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779 "2019-12-19T17:53:53Z")\
**Posts on this page:** 9\
**Page:** 1

<div class="post-metadata">

**Author:** ![Jia-Ming\_Lin](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jia-ming_lin/32/338_2.png) [@Jia-Ming\_Lin](https://discuss.pynq.io/u/Jia-Ming_Lin)\
**Post date:** [December 19, 2019, 5:53pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/1 "2019-12-19T17:53:53Z")

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I recently switch my works from PYNQ-Z2 to ZCU104.  
However, I get a problem on my first exercise, which is multiplying each elements in a given array by 3.  
I can receive the result, but it is incorrect. And any suggestion would be appreciated.

My input is

```auto
PynqBuffer([ 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
            64, 68, 72, 76], dtype=uint32)

```

the expected output is multiplying each element by 3.  
However, the result I obtained is

```auto
PynqBuffer([ 0, 0, 0, 0, 48, 0, 0, 0, 96, 0, 0, 0,
            144, 0, 0, 0, 192, 0, 0, 0], dtype=uint32)

```

My block design is

 ![Screenshot from 2019-12-20 01-45-42](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/10af017b3ec7c99b6a28774d0762719308475e75.png)

And the DMA configuration

 ![Screenshot from 2019-12-20 01-47-03](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/d4196b3784138c239809b12c0db9b2512a6f780c.png)

The C++ code is also attached with this post.

[array\_mul.cpp](https://discuss.pynq.io/uploads/short-url/5kwVLwbaZ3zL1IzNtoq4utQHA4B.cpp) (414 Bytes) [array\_mul.h](https://discuss.pynq.io/uploads/short-url/mzFCQ9ywpd2iSg8vKGK4ZyBlvee.h) (160 Bytes)

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<div class="post-metadata">

**Author:** ![patocarr](https://avatars.discourse-cdn.com/v4/letter/p/d2c977/32.png) [@patocarr](https://discuss.pynq.io/u/patocarr)\
**Post date:** [December 19, 2019, 6:00pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/2 "2019-12-19T18:00:08Z")

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@Jia-Ming_Lin

The issue could be in the SysGen IP and not the DMA. To test, you could replace the IP with a AXI-Stream FIFO hooked up in the same way as the IP and check the data you sent is identical as received.

Thanks,  
-Pat

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**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [December 19, 2019, 6:23pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/3 "2019-12-19T18:23:44Z")

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The issue is possibly a mismatch between software and hardware for the AXI slave ports on the PS8 block. The widths have to be 128-bits in order to be compatible with PYNQ - that should be the default but this has been known to change for reasons I don’t understand.

Peter

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<div class="post-metadata">

**Author:** ![Jia-Ming\_Lin](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jia-ming_lin/32/338_2.png) [@Jia-Ming\_Lin](https://discuss.pynq.io/u/Jia-Ming_Lin)\
**Post date:** [December 20, 2019, 3:08pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/4 "2019-12-20T15:08:08Z")

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Hi Peter, thank your for the reply,  
I did change the data width of AXI HP0 FPD and AXI HP1 FPD from 128(default) to 32.  
Do you mean the data width should be 128-bits?

Here is my original configurations of PS-PL interface

 ![Screenshot from 2019-12-20 23-11-41](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/1X/c58c89d7a2ce6f14315e66b53c0cbb6c6c8439ba.png)

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [December 20, 2019, 3:11pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/5 "2019-12-20T15:11:21Z")

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Yes - they should be 128. There has to be a match between that setting and what’s configured in software when the board boots and the block design. For the PYNQ boot files we keep the default of 128 so that’s what the block design should have as well.

Peter

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<div class="post-metadata">

**Author:** ![Jia-Ming\_Lin](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/jia-ming_lin/32/338_2.png) [@Jia-Ming\_Lin](https://discuss.pynq.io/u/Jia-Ming_Lin)\
**Post date:** [December 21, 2019, 3:03am UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/6 "2019-12-21T03:03:50Z")

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Hi Peter,  
I have one more question, I don’t understand why my input is

```auto
PynqBuffer([ 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
            64, 68, 72, 76], dtype=uint32)

```

then the output is

```auto
PynqBuffer([ 0, 0, 0, 0, 48, 0, 0, 0, 96, 0, 0, 0,
            144, 0, 0, 0, 192, 0, 0, 0], dtype=uint32)

```

, only multiply by 3 at 1,5,9,13,…4k+1 position, and all other are zero under my original settings.

My original settings are,  
Datawidth of slave HP on PS: 32 bits  
DMA Memory Map Access Datawidth: 32 bits  
DMA Streaming Datawidth: 32 bits  
Top function I/O Datawidth: 32bits

Thank you!

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [December 21, 2019, 8:15pm UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/7 "2019-12-21T20:15:37Z")

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One interesting thing about the way the way AXI works is that even if performing “narrow” transactions (i.e. the number of bytes is less than the bus width) the data will always appear on the wires that would be used if a full-width transaction was performed.

As an example, if I have a 128-bit wide bus and read 4 bytes at address 0x8 the data will be presented on wires 95:64.

There is a hardened data-width conversion block inside the processing system that converts between the internal 128-bit wide bus and the configuration seen in the block diagram. When configured in 128-bit mode (as is the case in the PYNQ image) it will send and receive the data as defined by the AXI standard shown above. In your design, however, only the lowest 32-bits are actually connected so only 1 in 4 32-bit words will be correctly sent into and out of the design. The other lines are not tied off so will default to 0.

Peter

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<div class="post-metadata">

**Author:** ![mattiasu96](https://avatars.discourse-cdn.com/v4/letter/m/f08c70/32.png) [@mattiasu96](https://discuss.pynq.io/u/mattiasu96)\
**Post date:** [May 9, 2021, 10:35am UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/8 "2021-05-09T10:35:51Z")

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It this still valid? If so, where I can find these informations on the documentation?

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<div class="post-metadata">

**Author:** ![PeterOgden](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/peterogden/32/55_2.png) [@PeterOgden](https://discuss.pynq.io/u/PeterOgden)\
**Post date:** [May 10, 2021, 8:05am UTC](https://discuss.pynq.io/t/using-axi-dma-on-zcu104/779/9 "2021-05-10T08:05:24Z")

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In 2.6 this is no longer the case - any port widths can be used. For older versions it is the default setting in Vivado.

Peter