# Using more pins for logictools in jupyter/Vivado

**URL:** <https://discuss.pynq.io/t/using-more-pins-for-logictools-in-jupyter-vivado/2755>\
**Category:** Support\
**Created:** [June 15, 2021, 3:45pm UTC](https://discuss.pynq.io/t/using-more-pins-for-logictools-in-jupyter-vivado/2755 "2021-06-15T15:45:19Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Ari\_C](https://avatars.discourse-cdn.com/v4/letter/a/85e7bf/32.png) [@Ari\_C](https://discuss.pynq.io/u/Ari_C)\
**Post date:** [June 15, 2021, 3:45pm UTC](https://discuss.pynq.io/t/using-more-pins-for-logictools-in-jupyter-vivado/2755/1 "2021-06-15T15:45:20Z")

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Hello,

I followed the tutorials in jupyter on how to use the Boolean generator and the pattern generator and was able to even make a D style flip-flop using the digital pins, pushbuttons, and LEDs on the PYNQ-Z2. However, I was wondering if there are more IO pins than the digital pins (D0-D19) and the switches, pushbuttons, and LEDs. My goal is to try and implement a LFSR using multiple D flip-flops and based on the number of pins available, I am not sure if it is feasible in jupyter. I am also currently working in Vivado and learning the basics to see if it would be possible to design an LSFR in that program instead. If it is something I would be able to do in either interface, I would appreciate it if someone could steer me in the right direction of how to do it.

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [July 14, 2021, 12:14pm UTC](https://discuss.pynq.io/t/using-more-pins-for-logictools-in-jupyter-vivado/2755/2 "2021-07-14T12:14:34Z")

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It would be better to do this in Vivado if you can.  
You should be able to find plenty of examples/tutorials on the internet.

E.g.  
VHDL LFSR (you may find better examples)  
[https://surf-vhdl.com/how-to-implement-an-lfsr-in-vhdl/](https://surf-vhdl.com/how-to-implement-an-lfsr-in-vhdl/)  
PYNQ creating a hardware design:  
[https://discuss.pynq.io/t/tutorial-creating-a-hardware-design-for-pynq/145/8](https://discuss.pynq.io/t/tutorial-creating-a-hardware-design-for-pynq/145/8)

Cathal