# Using vitis to create xclbin for the PYNQ-Z1 board

**URL:** <https://discuss.pynq.io/t/using-vitis-to-create-xclbin-for-the-pynq-z1-board/2096>\
**Category:** Support\
**Created:** [December 3, 2020, 2:14pm UTC](https://discuss.pynq.io/t/using-vitis-to-create-xclbin-for-the-pynq-z1-board/2096 "2020-12-03T14:14:53Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![Medrano](https://avatars.discourse-cdn.com/v4/letter/m/278dde/32.png) [@Medrano](https://discuss.pynq.io/u/Medrano)\
**Post date:** [December 3, 2020, 2:14pm UTC](https://discuss.pynq.io/t/using-vitis-to-create-xclbin-for-the-pynq-z1-board/2096/1 "2020-12-03T14:14:53Z")

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Hi there,  
I am using `vitis_hls` to build a kernel for a PYNQ-Z1 board. Currently, I am manually creating a block design in Vivado, which includes the aforementioned kernel.

Is it possible to use Vitis to create the bitstream (xclbin) for this board? I mean in the same way as bitstreams are created for AWS F1 instances.

Any example you could point me too?

Best,  
Medrano