# Vivado 2019.2 HWH parser issue

**URL:** <https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381>\
**Category:** Support\
**Created:** [June 16, 2020, 10:10pm UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381 "2020-06-16T22:10:41Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![SquaredS44](https://avatars.discourse-cdn.com/v4/letter/s/aca169/32.png) [@SquaredS44](https://discuss.pynq.io/u/SquaredS44)\
**Post date:** [June 16, 2020, 10:10pm UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381/1 "2020-06-16T22:10:41Z")

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Hello,

I am trying to create an overlay containing my custom IP.

However, I get the following error:`AttributeError: 'NoneType' object has no attribute 'get'`  
at line: `mod = it.find(".//PORTS//*[@DIR='I']" "//*[@INSTANCE='{0}'][@PORT='{1}']../../../..".format(self.ps_name, self.family_gpio))` of the hwh\_parser.py.

Looking online,I have come accross a few posts referring to some issues regarding the hdw/tcl parser with Vivado 2019.2 version.

How can I understand whether it is a parsing issue or anything is wrong with my design? The bitstream generation was successfully (?) completed without any errors.

Thank you,  
Sam

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**Author:** ![rock](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/rock/32/32_2.png) [@rock](https://discuss.pynq.io/u/rock)\
**Post date:** [June 19, 2020, 12:19am UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381/2 "2020-06-19T00:19:45Z")

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This might be because of the changes in 2019.2 HWH file. We are currently working towards the next release.

Maybe you can port over your project back to 2019.1 and see if HWH parser works? Otherwise we will have to wait until we are testing our next release.

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**Author:** ![SquaredS44](https://avatars.discourse-cdn.com/v4/letter/s/aca169/32.png) [@SquaredS44](https://discuss.pynq.io/u/SquaredS44)\
**Post date:** [June 20, 2020, 12:14pm UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381/3 "2020-06-20T12:14:52Z")

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Hello, I tried implementing the same design with Vivado 2018.3 and although the bistream generation completes successfully I still get an empty IP dict when using the _ **.tcl file** _ or the error: ` AttributeError: 'NoneType' object has no attribute 'get'` at line: `din = int(mod.find(".//*[@NAME='DIN_FROM']").get('VALUE'))` of the `self.add_gpio()` function in the **overlay.py** script when using the _ **HWH file** _. Could you please help me figure out what’s causing this issue? Thank you.

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**Author:** ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)\
**Post date:** [June 22, 2020, 6:07am UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381/4 "2020-06-22T06:07:59Z")

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Can you send a copy of your Tcl, and an image of your block diagram?

Cathal

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**Author:** ![SquaredS44](https://avatars.discourse-cdn.com/v4/letter/s/aca169/32.png) [@SquaredS44](https://discuss.pynq.io/u/SquaredS44)\
**Post date:** [June 28, 2020, 1:15pm UTC](https://discuss.pynq.io/t/vivado-2019-2-hwh-parser-issue/1381/5 "2020-06-28T13:15:03Z")

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Hello @cathalmccabe,  
sorry for the late reply.

I solved the issue using **Vivado 2018.3.**

It seems like using the .tcl and .bit file from the HDL wrapper bitstream generation does not work. Using the .bit file from the HDL wrapper bitstream generation and the “export hardware” .tcl file works.

What I mean by that, for example, is that is your HDL wrapper is “a\_wrapper”, using _a\_wrapper.bit_ and _a\_wrapper.tcl_ does not work. But using _a\_wrapper.bit_ and _a.tcl_ (renamed to match the .bit file), it works.

Sorry if I am saying something obvious, I am a new to FPGA design.

Thank you for your help.

Sam