# When I used custom

**URL:** <https://discuss.pynq.io/t/when-i-used-custom/7336>\
**Category:** Support\
**Created:** [July 29, 2024, 7:50am UTC](https://discuss.pynq.io/t/when-i-used-custom/7336 "2024-07-29T07:50:46Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![cydiazero](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cydiazero/32/6221_2.png) [@cydiazero](https://discuss.pynq.io/u/cydiazero)\
**Post date:** [July 29, 2024, 7:50am UTC](https://discuss.pynq.io/t/when-i-used-custom/7336/1 "2024-07-29T07:50:46Z")

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Hello, I have problem…  
I use Pynq-z2 board is installed v3.0.1 image and my Vivado version is 2024.1  
I want use my custom accelerator that was written by Verilog HDL.  
So, I tried a tutorial of Verilog Module Overlay. I referred a post, “[Tutorial: Creating a new Verilog Module Overlay](https://discuss.pynq.io/t/tutorial-creating-a-new-verilog-module-overlay/1530)”  
But, I have a problem when I use Overlay.my\_verilog\_custom\_ip.write function.  
When I use that function, the Jupyter notebook is looping (“[\*]”) and notify connection failed few second later… The read function is work.  
So, I tried using MIMO module. But It is not solution.

 ![스크린샷 2024-07-29 오후 3.15.09](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/5/52e3516541719c1b873a6e7b25d02bd8cb4cd848.png)  
(I modify 0x0C. That is my intention.)

How to solve this problem?

Thank you.

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**Author:** ![mtsanic](https://avatars.discourse-cdn.com/v4/letter/m/bb73d2/32.png) [@mtsanic](https://discuss.pynq.io/u/mtsanic)\
**Post date:** [July 29, 2024, 1:17pm UTC](https://discuss.pynq.io/t/when-i-used-custom/7336/2 "2024-07-29T13:17:17Z")

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Hi @cydiazero ,

Are you sure your IP is memory mapped?

Best

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**Author:** ![cydiazero](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cydiazero/32/6221_2.png) [@cydiazero](https://discuss.pynq.io/u/cydiazero)\
**Post date:** [July 29, 2024, 4:10pm UTC](https://discuss.pynq.io/t/when-i-used-custom/7336/3 "2024-07-29T16:10:18Z")

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Hello @mtsanic , Thank you for your interest in my question.  
But, I don’t understand “your IP is memory mapped?”  
Are you asking me “Modify AXI Interface” or “Set IP Register in tab of Addressing and Memory”?  
I applied both.

I modify a AXI Interface of my IP.  
In my code, I added my module “adder”.  
 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/f/f945bedb29c7184fefb4da3221c0388c4cd3ac5c.png)  
and I modify the section of AXI write channel.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/0/0bf21026c74c8f89707542c24c7f3b9ef3b30db8.png)

There was no word in that tutorial, I added the infomations of four registers in Addressing and Memory section.

 ![image](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/1/10327a459c3e7f57093a1fe613e747fc4e0baae0.png)

Thank you!

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<div class="post-metadata">

**Author:** ![cydiazero](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cydiazero/32/6221_2.png) [@cydiazero](https://discuss.pynq.io/u/cydiazero)\
**Post date:** [August 2, 2024, 8:07am UTC](https://discuss.pynq.io/t/when-i-used-custom/7336/4 "2024-08-02T08:07:35Z")

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I found solution.  
The problem is vivado 2024.1.  
When I try vivado 2022.2, It is working!!

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**Author:** ![marioruiz](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/marioruiz/32/2177_2.png) [@marioruiz](https://discuss.pynq.io/u/marioruiz)\
**Post date:** [August 2, 2024, 10:04am UTC](https://discuss.pynq.io/t/when-i-used-custom/7336/5 "2024-08-02T10:04:59Z")

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