# ZCU111 DAC loopback problem

**URL:** <https://discuss.pynq.io/t/zcu111-dac-loopback-problem/2235>\
**Category:** Support\
**Created:** [January 12, 2021, 5:29pm UTC](https://discuss.pynq.io/t/zcu111-dac-loopback-problem/2235 "2021-01-12T17:29:52Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![damien.fruleux](https://avatars.discourse-cdn.com/v4/letter/d/2acd7d/32.png) [@damien.fruleux](https://discuss.pynq.io/u/damien.fruleux)\
**Post date:** [January 12, 2021, 5:29pm UTC](https://discuss.pynq.io/t/zcu111-dac-loopback-problem/2235/1 "2021-01-12T17:29:52Z")

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Hello,

I’m trying to use the DAC of a ZCU111 with Pynq, and I have a “loopback” problem.

In the capture of my block design, you can see that I am using 2 DMA, and I generate a sine with PS (for this example, I’m using only 1 clock generated by the PLL for the DMAs and the DACs) :

- DMA3 is used to directly stream the content to the DAC. It’s working very well : I have 1 sine, and I need to use the capture mode of the oscilloscope to see it.  
I can send 16 samples (1 stream), 32 (2 streams)… (I note that I have some little technical problems if I try to send more than 32 samples, it is not the question right know, but it is very strange).

- DMA2 is the same, but I add a FIFO for the example. It’s working, but I don’t have just 1 sine, but an infinite repetition of it ! The oscilloscope just print infinite sine. It’s like a loopback.  
Moreover, I can only send 16 samples (so 1 stream), and the signal is repeating itself. If I use more samples, the signal is cut, and I can only see the first 16 samples. If I use less, like 8, I can see my 8 samples, and 8 “zeros”, it is normal. The problem is the same if I’m using a stream broadcaster instead of a FIFO. So I don’t think the FIFO repeat the signal, but the DMA is continuously read from memory, without “delete” samples after each “read & transfer”.

I’m using [DMA — Python productivity for Zynq (Pynq)](https://pynq.readthedocs.io/en/v2.6.1/pynq_libraries/dma.html) to generate a buffer & transfert data.

My goal is to post on GitHub/GitLab a development platform for ZCU111 and the RF part (DAC, ADC… and probably 4\*SFP25) with Pynq, but without any external tools (Stratclyde used LabView tools, so it is useless for my project). I hope it can help others peoples 🙂

I already make a post on Xilinx forum ([https://forums.xilinx.com/t5/Versal-and-UltraScale/ZCU111-DAC-loopback/td-p/1184624](https://forums.xilinx.com/t5/Versal-and-UltraScale/ZCU111-DAC-loopback/td-p/1184624)) but I don’t have any answers.

Thank you very very much for your help.

Damien

[design\_for\_pynq\_forum.pdf](https://discuss.pynq.io/uploads/short-url/4ZEzhSrvbfZ5delSDTiZR77S69h.pdf) (209.5 KB)