# Zynq AXI HP Interface

**URL:** https://discuss.pynq.io/t/zynq-axi-hp-interface/3409
**Category:** Support
**Created:** [December 9, 2021, 7:00am UTC](https://discuss.pynq.io/t/zynq-axi-hp-interface/3409 "2021-12-09T07:00:56Z")
**Posts on this page:** 2
**Page:** 1

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### Author: ![Anubhav\_Agarwal](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/anubhav_agarwal/32/2645_2.png) [@Anubhav\_Agarwal](https://discuss.pynq.io/u/Anubhav_Agarwal)
#### Post date: [December 9, 2021, 7:00am UTC](https://discuss.pynq.io/t/zynq-axi-hp-interface/3409/1 "2021-12-09T07:00:56Z")

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Hi everyone!  
I am using Pynq-Z2 board along with Version 2020.2 of Xilinx design tools.

I have created a custom IP in Vitis HLS to perform multiplication operation between two arrays w and x . The arrays have been passed as a pointer with m\_axi mode. The HLS code is attached in the following image.

After exporting the RTL, I add it to Vivado. Then a new block diagram is created where I add Zynq and the custom IP which I have created. After running connection automation, I get the following warnings. I have enabled HP0 and GP0 interfaces under PS-PL configuration in Zynq block. Could anyone please tell how can we resolve the following addressing issues.

 ![pynq-forum1](https://us1.discourse-cdn.com/flex019/uploads/pynq1/original/2X/2/20c2e39421aac74a84354c137360e06defc0b21b.jpeg)

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### Author: ![cathalmccabe](https://sea1.discourse-cdn.com/flex019/user_avatar/discuss.pynq.io/cathalmccabe/32/3348_2.png) [@cathalmccabe](https://discuss.pynq.io/u/cathalmccabe)
#### Post date: [December 9, 2021, 8:09am UTC](https://discuss.pynq.io/t/zynq-axi-hp-interface/3409/2 "2021-12-09T08:09:59Z")

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The warning is indicating a problem with your address map. Did you check this? There should be a tab for this beside the tab for you block design.  
Adding more info and proper screenshots would help.

Cathal