#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Thu Apr 11 22:34:53 2024
# Process ID: 18280
# Current directory: C:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk
# Command line: vivado.exe -mode batch -source make_bitstream.tcl -notrace
# Log file: C:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/vivado.log
# Journal file: C:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk\vivado.jou
#-----------------------------------------------------------
Sourcing tcl script 'C:/Users/seamu/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source make_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Capstone/rfsoc_qpsk/boards/ip/iprepo'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 1027.539 ; gain = 0.000
Reading block design file <C:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.srcs/sources_1/bd/rfsoc_qpsk/rfsoc_qpsk.bd>...
Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - axi_intc_fpd
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - interrupt_concat_fpd
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - pl_leds_concat
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_rx
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_0
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_1
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_1
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_rx_csync
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_rx_dec
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_rx_rrc
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_rx_tsync
Adding component instance block -- UoS:SysGen:axi_qpsk_rx_csync:1.1 - qpsk_rx_csync
Adding component instance block -- UoS:SysGen:axi_qpsk_rx_dec:1.1 - qpsk_rx_dec
Adding component instance block -- UoS:SysGen:axi_qpsk_rx_rrc:1.1 - qpsk_rx_rrc
Adding component instance block -- UoS:SysGen:axi_qpsk_rx_tsync:1.1 - qpsk_rx_tsync
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_128
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_256
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_pl
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - smartconnect_0
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:smartconnect:1.0 - axi_smc_1
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_tx
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_tx_fft
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_tx_symbol
Adding component instance block -- xilinx.com:ip:axi_dma:7.1 - dma_tx_time
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_0
Adding component instance block -- xilinx.com:ip:axis_data_fifo:2.0 - axis_data_fifo_1
Adding component instance block -- xilinx.com:user:axis_signal_join:1.0 - axis_signal_join_0
Adding component instance block -- xilinx.com:user:axis_signal_splitter:1.0 - axis_signal_splitter_1
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_1
Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - ps8_0_axi_periph
Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar
Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds
Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc
Adding component instance block -- UoS:RFSoC:axi_qpsk_tx:5.3 - qpsk_tx
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_128
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_25_6
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - reset_pl
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps8_0_99M
Adding component instance block -- xilinx.com:ip:usp_rf_data_converter:2.4 - usp_rf_data_converter_0
INFO: Ultrascale+ RF Data Converter instance: Clock port 'adc2_clk' frequency is set to 64000000
INFO: Ultrascale+ RF Data Converter instance: Clock port 'dac2_clk' frequency is set to 128000000
Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - zynq_ultra_ps_e_0
Successfully read diagram <rfsoc_qpsk> from block design file <./block_design/block_design.srcs/sources_1/bd/rfsoc_qpsk/rfsoc_qpsk.bd>
open_bd_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1027.539 ; gain = 0.000
INFO: [BD 41-1662] The design 'rfsoc_qpsk.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/synth/rfsoc_qpsk.vhd
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/sim/rfsoc_qpsk.vhd
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/hdl/rfsoc_qpsk_wrapper.vhd
INFO: [BD 41-1662] The design 'rfsoc_qpsk.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/synth/rfsoc_qpsk.vhd
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/sim/rfsoc_qpsk.vhd
VHDL Output written to : c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/hdl/rfsoc_qpsk_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_fpd .
INFO: [BD 41-1029] Generation completed for the IP Integrator block interrupt_concat_fpd .
INFO: [BD 41-1029] Generation completed for the IP Integrator block pl_leds_concat .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_ds_0/rfsoc_qpsk_auto_ds_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_pc_0/rfsoc_qpsk_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_0/rfsoc_qpsk_auto_cc_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m00_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_1/rfsoc_qpsk_auto_cc_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m01_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_2/rfsoc_qpsk_auto_cc_2_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m02_couplers/auto_cc .
ERROR: [Common 17-232] Could not create slave interpreter '::ipgen_iptclns'.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2020.2/data/ip/xilinx/axi_clock_converter_v2_1/ttcl/ooc_xdc.ttcl': 
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP 'qpsk_rx/axi_interconnect_0/m03_couplers/auto_cc'. Failed to generate 'Verilog Synthesis' outputs: 
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'qpsk_rx/axi_interconnect_0/m03_couplers/auto_cc'. Failed to generate 'Verilog Synthesis' outputs: 
ERROR: [BD 41-1030] Generation failed for the IP Integrator block qpsk_rx/axi_interconnect_0/m03_couplers/auto_cc 
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_4/rfsoc_qpsk_auto_cc_4_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m04_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_5/rfsoc_qpsk_auto_cc_5_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m05_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_6/rfsoc_qpsk_auto_cc_6_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m06_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_7/rfsoc_qpsk_auto_cc_7_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/axi_interconnect_0/m07_couplers/auto_cc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/clk_rx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/decimate_logic/axis_data_fifo_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/decimate_logic/axis_data_fifo_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/decimate_logic/fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/decimate_logic/fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/dma_rx_csync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/dma_rx_dec .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/dma_rx_rrc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/dma_rx_tsync .
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_csync_0' detected a language mismatch between 'Verilog Synthesis Wrapper' and 'VHDL Synthesis' output products. Please check with the IP provider to see if this is expected.
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_csync_0' detected a language mismatch between 'Verilog Simulation Wrapper' and 'VHDL Simulation' output products. Please check with the IP provider to see if this is expected.
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_csync_c_addsub_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_csync_c_counter_binary_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_csync_cmpy_v6_0_i0 (Complex Multiplier 6.0) from revision 18 to revision 19
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_csync_cmpy_v6_0_i1 (Complex Multiplier 6.0) from revision 18 to revision 19
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_csync_fifo_generator_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_csync_mult_gen_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_csync_mult_gen_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_csync_xfft_v9_1_i0 (Fast Fourier Transform 9.1) from revision 4 to revision 5
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/qpsk_rx_csync .
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_dec_0' detected a language mismatch between 'Verilog Synthesis Wrapper' and 'VHDL Synthesis' output products. Please check with the IP provider to see if this is expected.
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_dec_0' detected a language mismatch between 'Verilog Simulation Wrapper' and 'VHDL Simulation' output products. Please check with the IP provider to see if this is expected.
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_dec_c_counter_binary_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_dec_cic_compiler_v4_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_dec_cic_compiler_v4_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_dec_fifo_generator_i0 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_dec_fir_compiler_v7_2_i0 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_dec_fir_compiler_v7_2_i1 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/qpsk_rx_dec .
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_rrc_0' detected a language mismatch between 'Verilog Synthesis Wrapper' and 'VHDL Synthesis' output products. Please check with the IP provider to see if this is expected.
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_rrc_0' detected a language mismatch between 'Verilog Simulation Wrapper' and 'VHDL Simulation' output products. Please check with the IP provider to see if this is expected.
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_rrc_c_counter_binary_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_rrc_fifo_generator_i0 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_rrc_fir_compiler_v7_2_i0 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_rrc_fir_compiler_v7_2_i1 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_rx_rrc_fir_compiler_v7_2_i2 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/qpsk_rx_rrc .
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_tsync_0' detected a language mismatch between 'Verilog Synthesis Wrapper' and 'VHDL Synthesis' output products. Please check with the IP provider to see if this is expected.
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_rx_tsync_0' detected a language mismatch between 'Verilog Simulation Wrapper' and 'VHDL Simulation' output products. Please check with the IP provider to see if this is expected.
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i2 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i3 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i4 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i5 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i6 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i7 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i8 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_addsub_v12_0_i9 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_counter_binary_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_c_counter_binary_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_fifo_generator_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i2 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i3 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i4 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_rx_tsync_mult_gen_v12_0_i5 to use current project options
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/qpsk_rx_tsync .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/reset_128 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/reset_256 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/reset_pl .
Exporting to file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_smartconnect_0_0/bd_0/hw_handoff/rfsoc_qpsk_smartconnect_0_0.hwh
Generated Block Design Tcl file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_smartconnect_0_0/bd_0/hw_handoff/rfsoc_qpsk_smartconnect_0_0_bd.tcl
Generated Hardware Definition File c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_smartconnect_0_0/bd_0/synth/rfsoc_qpsk_smartconnect_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/smartconnect_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_rx/xlconcat_0 .
Exporting to file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_axi_smc_1_0/bd_0/hw_handoff/rfsoc_qpsk_axi_smc_1_0.hwh
Generated Block Design Tcl file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_axi_smc_1_0/bd_0/hw_handoff/rfsoc_qpsk_axi_smc_1_0_bd.tcl
Generated Hardware Definition File c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_axi_smc_1_0/bd_0/synth/rfsoc_qpsk_axi_smc_1_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/axi_smc_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/clk_tx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/dma_tx_fft .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/dma_tx_symbol .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/dma_tx_time .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/axis_data_fifo_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/axis_data_fifo_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/axis_signal_join_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/axis_signal_splitter_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/interpolate_logic/fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/xbar .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_ds_1/rfsoc_qpsk_auto_ds_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_pc_1/rfsoc_qpsk_auto_pc_1_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/s00_couplers/auto_pc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_8/rfsoc_qpsk_auto_cc_8_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/m00_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_9/rfsoc_qpsk_auto_cc_9_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/m02_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_10/rfsoc_qpsk_auto_cc_10_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/m03_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file 'c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/ip/rfsoc_qpsk_auto_cc_11/rfsoc_qpsk_auto_cc_11_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/ps8_0_axi_periph/m04_couplers/auto_cc .
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_tx_0' detected a language mismatch between 'Verilog Synthesis Wrapper' and 'VHDL Synthesis' output products. Please check with the IP provider to see if this is expected.
WARNING: [IP_Flow 19-519] IP 'rfsoc_qpsk_qpsk_tx_0' detected a language mismatch between 'Verilog Simulation Wrapper' and 'VHDL Simulation' output products. Please check with the IP provider to see if this is expected.
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_c_addsub_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_c_counter_binary_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_c_counter_binary_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_cic_compiler_v4_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_fifo_generator_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_fifo_generator_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_fifo_generator_i2 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_tx_fir_compiler_v7_2_i0 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_tx_fir_compiler_v7_2_i1 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_tx_fir_compiler_v7_2_i2 (FIR Compiler 7.2) from revision 14 to revision 15
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_mult_gen_v12_0_i0 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_mult_gen_v12_0_i1 to use current project options
INFO: [IP_Flow 19-3420] Updated axi_qpsk_tx_mult_gen_v12_0_i2 to use current project options
INFO: [IP_Flow 19-3422] Upgraded axi_qpsk_tx_xfft_v9_1_i0 (Fast Fourier Transform 9.1) from revision 4 to revision 5
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/qpsk_tx .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/reset_128 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/reset_25_6 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/reset_pl .
INFO: [BD 41-1029] Generation completed for the IP Integrator block qpsk_tx/xlconcat_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps8_0_99M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block usp_rf_data_converter_0 .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] rfsoc_qpsk_zynq_ultra_ps_e_0_0: 
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM1_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP1_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP2_FPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block zynq_ultra_ps_e_0 .
Exporting to file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/hw_handoff/rfsoc_qpsk.hwh
Generated Block Design Tcl file c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/hw_handoff/rfsoc_qpsk_bd.tcl
Generated Hardware Definition File c:/Capstone/rfsoc_qpsk/boards/RFSoC4x2/rfsoc_qpsk/block_design/block_design.gen/sources_1/bd/rfsoc_qpsk/synth/rfsoc_qpsk.hwdef
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_10
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_11
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_2
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_3
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_4
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_5
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_6
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_7
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_8
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_cc_9
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_ds_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_ds_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_pc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_auto_pc_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axi_intc_fpd_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axi_smc_1_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_data_fifo_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_data_fifo_0_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_data_fifo_1_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_data_fifo_1_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_signal_join_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_axis_signal_splitter_1_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_clk_rx_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_clk_tx_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_rx_csync_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_rx_dec_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_rx_rrc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_rx_tsync_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_tx_fft_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_tx_symbol_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_dma_tx_time_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_fir_compiler_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_fir_compiler_0_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_fir_compiler_1_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_fir_compiler_1_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_qpsk_rx_csync_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_qpsk_rx_dec_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_qpsk_rx_rrc_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_qpsk_rx_tsync_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_qpsk_tx_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_128_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_128_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_256_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_25_6_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_pl_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_reset_pl_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_rst_ps8_0_99M_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_smartconnect_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_usp_rf_data_converter_0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_xbar_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_xbar_1
INFO: [IP_Flow 19-7066] Running IP cache check for IP rfsoc_qpsk_zynq_ultra_ps_e_0_0
ERROR: [Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.
INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 22:37:24 2024...