/****************************************************************************** * Copyright (C) 2021 Xilinx, Inc. All rights reserved. * SPDX-License-Identifier: MIT ******************************************************************************/ /**************************** Type Definitions *******************************/ /* #define XRFdc_IsADC4GSPS(InstPtr) XRFdc_IsHighSpeedADC(InstPtr, 0) */ typedef unsigned int u32; typedef unsigned short u16; typedef unsigned char u8; typedef signed int s32; typedef signed short s16; typedef unsigned long u64; typedef signed long s64; typedef unsigned long metal_phys_addr_t; /** * The handler data type allows the user to define a callback function to * respond to interrupt events in the system. This function is executed * in interrupt context, so amount of processing should be minimized. * * @param CallBackRef is the callback reference passed in by the upper * layer when setting the callback functions, and passed back to * the upper layer when the callback is invoked. Its type is * not important to the driver, so it is a void pointer. * @param Type indicates ADC/DAC. * @param Tile_Id indicates Tile number (0-3). * @param Block_Id indicates Block number (0-3). * @param StatusEvent indicates one or more interrupt occurred. */ typedef void (*XRFdc_StatusHandler)(void *CallBackRef, u32 Type, u32 Tile_Id, u32 Block_Id, u32 StatusEvent); /** * PLL settings. */ typedef struct { u32 Enabled; /* PLL Enables status (not a setter) */ double RefClkFreq; double SampleRate; u32 RefClkDivider; u32 FeedbackDivider; u32 OutputDivider; u32 FractionalMode; /* Fractional mode is currently not supported */ u64 FractionalData; /* Fractional data is currently not supported */ u32 FractWidth; /* Fractional width is currently not supported */ } XRFdc_PLL_Settings; /** * ClkIntraTile Settings. */ typedef struct { u8 SourceTile; u8 PLLEnable; XRFdc_PLL_Settings PLLSettings; u8 DivisionFactor; u8 Delay; u8 DistributedClock; } XRFdc_Tile_Clock_Settings; /** * Clk Distribution. */ typedef struct { u8 Enabled; u8 DistributionSource; u8 UpperBound; u8 LowerBound; u8 MaxDelay; u8 MinDelay; u8 IsDelayBalanced; } XRFdc_Distribution; /** * Clk Distribution Settings. */ typedef struct { XRFdc_Tile_Clock_Settings DAC[4]; XRFdc_Tile_Clock_Settings ADC[4]; XRFdc_Distribution DistributionStatus[8]; } XRFdc_Distribution_Settings; /** * MTS DTC Settings. */ typedef struct { u32 RefTile; u32 IsPLL; int Target[4]; int Scan_Mode; int DTC_Code[4]; int Num_Windows[4]; int Max_Gap[4]; int Min_Gap[4]; int Max_Overlap[4]; } XRFdc_MTS_DTC_Settings; /** * MTS Sync Settings. */ typedef struct { u32 RefTile; u32 Tiles; int Target_Latency; int Offset[4]; int Latency[4]; int Marker_Delay; int SysRef_Enable; XRFdc_MTS_DTC_Settings DTC_Set_PLL; XRFdc_MTS_DTC_Settings DTC_Set_T1; } XRFdc_MultiConverter_Sync_Config; /** * MTS Marker Struct. */ typedef struct { u32 Count[4]; u32 Loc[4]; } XRFdc_MTS_Marker; /** * ADC Signal Detect Settings. */ typedef struct { u8 Mode; u8 TimeConstant; u8 Flush; u8 EnableIntegrator; u16 HighThreshold; u16 LowThreshold; u16 HighThreshOnTriggerCnt; /* the number of times value must exceed HighThreshold before turning on*/ u16 HighThreshOffTriggerCnt; /* the number of times value must be less than HighThreshold before turning off*/ u16 LowThreshOnTriggerCnt; /* the number of times value must exceed LowThreshold before turning on*/ u16 LowThreshOffTriggerCnt; /* the number of times value must be less than LowThreshold before turning off*/ u8 HysteresisEnable; } XRFdc_Signal_Detector_Settings; /** * QMC settings. */ typedef struct { u32 EnablePhase; u32 EnableGain; double GainCorrectionFactor; double PhaseCorrectionFactor; s32 OffsetCorrectionFactor; u32 EventSource; } XRFdc_QMC_Settings; /** * Coarse delay settings. */ typedef struct { u32 CoarseDelay; u32 EventSource; } XRFdc_CoarseDelay_Settings; /** * Mixer settings. */ typedef struct { double Freq; double PhaseOffset; u32 EventSource; u32 CoarseMixFreq; u32 MixerMode; u8 FineMixerScale; /* NCO output scale, valid values 0,1 and 2 */ u8 MixerType; } XRFdc_Mixer_Settings; /** * ADC block Threshold settings. */ typedef struct { u32 UpdateThreshold; /* Selects which threshold to update */ u32 ThresholdMode[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */ u32 ThresholdAvgVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */ u32 ThresholdUnderVal[2]; /* Entry 0 for Threshold0 and 1 for Threshold1 */ u32 ThresholdOverVal[2]; /* Entry 0 is for Threshold0 and 1 for Threshold1 */ } XRFdc_Threshold_Settings; /** * RFSoC Calibration coefficients generic struct */ typedef struct { u32 Coeff0; u32 Coeff1; u32 Coeff2; u32 Coeff3; u32 Coeff4; u32 Coeff5; u32 Coeff6; u32 Coeff7; } XRFdc_Calibration_Coefficients; /** * RFSoC Power Mode settings */ typedef struct { u32 DisableIPControl; /*Disables IP RTS control of the power mode*/ u32 PwrMode; /*The power mode*/ } XRFdc_Pwr_Mode_Settings; /** * RFSoC DSA settings */ typedef struct { u32 DisableRTS; /*Disables RTS control of DSA attenuation*/ float Attenuation; /*Attenuation*/ } XRFdc_DSA_Settings; /** * RFSoC Calibration freeze settings struct */ typedef struct { u32 CalFrozen; /*Status indicates calibration freeze state*/ u32 DisableFreezePin; /*Disable the calibration freeze pin*/ u32 FreezeCalibration; /*Setter for freezing*/ } XRFdc_Cal_Freeze_Settings; /** * RFSoC Tile status. */ typedef struct { u32 IsEnabled; /* 1, if tile is enabled, 0 otherwise */ u32 TileState; /* Indicates Tile Current State */ u8 BlockStatusMask; /* Bit mask for block status, 1 indicates block enable */ u32 PowerUpState; u32 PLLState; } XRFdc_TileStatus; /** * RFSoC Data converter IP status. */ typedef struct { XRFdc_TileStatus DACTileStatus[4]; XRFdc_TileStatus ADCTileStatus[4]; u32 State; } XRFdc_IPStatus; /** * status of DAC or ADC blocks in the RFSoC Data converter. */ typedef struct { double SamplingFreq; u32 AnalogDataPathStatus; u32 DigitalDataPathStatus; u8 DataPathClocksStatus; /* Indicates all required datapath clocks are enabled or not, 1 if all clocks enabled, 0 otherwise */ u8 IsFIFOFlagsEnabled; /* Indicates FIFO flags enabled or not, 1 if all flags enabled, 0 otherwise */ u8 IsFIFOFlagsAsserted; /* Indicates FIFO flags asserted or not, 1 if all flags asserted, 0 otherwise */ } XRFdc_BlockStatus; /** * DAC block Analog DataPath Config settings. */ typedef struct { u32 BlockAvailable; u32 InvSyncEnable; u32 MixMode; u32 DecoderMode; } XRFdc_DACBlock_AnalogDataPath_Config; /** * DAC block Digital DataPath Config settings. */ typedef struct { u32 MixerInputDataType; u32 DataWidth; u32 InterpolationMode; u32 FifoEnable; u32 AdderEnable; u32 MixerType; } XRFdc_DACBlock_DigitalDataPath_Config; /** * ADC block Analog DataPath Config settings. */ typedef struct { u32 BlockAvailable; u32 MixMode; } XRFdc_ADCBlock_AnalogDataPath_Config; /** * ADC block Digital DataPath Config settings. */ typedef struct { u32 MixerInputDataType; u32 DataWidth; u32 DecimationMode; u32 FifoEnable; u32 MixerType; } XRFdc_ADCBlock_DigitalDataPath_Config; /** * DAC Tile Config structure. */ typedef struct { u32 Enable; u32 PLLEnable; double SamplingRate; double RefClkFreq; double FabClkFreq; u32 FeedbackDiv; u32 OutputDiv; u32 RefClkDiv; u32 MultibandConfig; double MaxSampleRate; u32 NumSlices; XRFdc_DACBlock_AnalogDataPath_Config DACBlock_Analog_Config[4]; XRFdc_DACBlock_DigitalDataPath_Config DACBlock_Digital_Config[4]; } XRFdc_DACTile_Config; /** * ADC Tile Config Structure. */ typedef struct { u32 Enable; /* Tile Enable status */ u32 PLLEnable; /* PLL enable Status */ double SamplingRate; double RefClkFreq; double FabClkFreq; u32 FeedbackDiv; u32 OutputDiv; u32 RefClkDiv; u32 MultibandConfig; double MaxSampleRate; u32 NumSlices; XRFdc_ADCBlock_AnalogDataPath_Config ADCBlock_Analog_Config[4]; XRFdc_ADCBlock_DigitalDataPath_Config ADCBlock_Digital_Config[4]; } XRFdc_ADCTile_Config; /** * RFdc Config Structure. */ typedef struct { u32 DeviceId; metal_phys_addr_t BaseAddr; u32 ADCType; /* ADC Type 4GSPS or 2GSPS*/ u32 MasterADCTile; /* ADC master Tile */ u32 MasterDACTile; /* DAC Master Tile */ u32 ADCSysRefSource; u32 DACSysRefSource; u32 IPType; u32 SiRevision; XRFdc_DACTile_Config DACTile_Config[4]; XRFdc_ADCTile_Config ADCTile_Config[4]; } XRFdc_Config; /** * DAC Block Analog DataPath Structure. */ typedef struct { u32 Enabled; /* DAC Analog Data Path Enable */ u32 MixedMode; double TerminationVoltage; double OutputCurrent; u32 InverseSincFilterEnable; u32 DecoderMode; void *FuncHandler; u32 NyquistZone; u8 AnalogPathEnabled; u8 AnalogPathAvailable; XRFdc_QMC_Settings QMC_Settings; XRFdc_CoarseDelay_Settings CoarseDelay_Settings; } XRFdc_DACBlock_AnalogDataPath; /** * DAC Block Digital DataPath Structure. */ typedef struct { u32 MixerInputDataType; u32 DataWidth; int ConnectedIData; int ConnectedQData; u32 InterpolationFactor; u8 DigitalPathEnabled; u8 DigitalPathAvailable; XRFdc_Mixer_Settings Mixer_Settings; } XRFdc_DACBlock_DigitalDataPath; /** * ADC Block Analog DataPath Structure. */ typedef struct { u32 Enabled; /* ADC Analog Data Path Enable */ XRFdc_QMC_Settings QMC_Settings; XRFdc_CoarseDelay_Settings CoarseDelay_Settings; XRFdc_Threshold_Settings Threshold_Settings; u32 NyquistZone; u8 CalibrationMode; u8 AnalogPathEnabled; u8 AnalogPathAvailable; } XRFdc_ADCBlock_AnalogDataPath; /** * ADC Block Digital DataPath Structure. */ typedef struct { u32 MixerInputDataType; u32 DataWidth; u32 DecimationFactor; int ConnectedIData; int ConnectedQData; u8 DigitalPathEnabled; u8 DigitalPathAvailable; XRFdc_Mixer_Settings Mixer_Settings; } XRFdc_ADCBlock_DigitalDataPath; /** * DAC Tile Structure. */ typedef struct { u32 TileBaseAddr; /* Tile BaseAddress*/ u32 NumOfDACBlocks; /* Number of DAC block enabled */ XRFdc_PLL_Settings PLL_Settings; u8 MultibandConfig; XRFdc_DACBlock_AnalogDataPath DACBlock_Analog_Datapath[4]; XRFdc_DACBlock_DigitalDataPath DACBlock_Digital_Datapath[4]; } XRFdc_DAC_Tile; /** * ADC Tile Structure. */ typedef struct { u32 TileBaseAddr; u32 NumOfADCBlocks; /* Number of ADC block enabled */ XRFdc_PLL_Settings PLL_Settings; u8 MultibandConfig; XRFdc_ADCBlock_AnalogDataPath ADCBlock_Analog_Datapath[4]; XRFdc_ADCBlock_DigitalDataPath ADCBlock_Digital_Datapath[4]; } XRFdc_ADC_Tile; /** * RFdc Structure. */ typedef struct { XRFdc_Config RFdc_Config; /* Config Structure */ u32 IsReady; u32 ADC4GSPS; metal_phys_addr_t BaseAddr; /* BaseAddress */ struct metal_io_region *io; /* Libmetal IO structure */ struct metal_device *device; /* Libmetal device structure */ XRFdc_DAC_Tile DAC_Tile[4]; XRFdc_ADC_Tile ADC_Tile[4]; XRFdc_StatusHandler StatusHandler; /* Event handler function */ void *CallBackRef; /* Callback reference for event handler */ u8 UpdateMixerScale; /* Set to 1, if user overwrite mixer scale */ } XRFdc; /***************** Macros (Inline Functions) Definitions *********************/ #define XRFDC_ADC_TILE 0U #define XRFDC_DAC_TILE 1U /* MTS Error Codes */ #define XRFDC_MTS_OK 0U #define XRFDC_MTS_NOT_SUPPORTED 1U #define XRFDC_MTS_TIMEOUT 2U #define XRFDC_MTS_MARKER_RUN 4U #define XRFDC_MTS_MARKER_MISM 8U #define XRFDC_MTS_DELAY_OVER 16U #define XRFDC_MTS_TARGET_LOW 32U #define XRFDC_MTS_IP_NOT_READY 64U #define XRFDC_MTS_DTC_INVALID 128U #define XRFDC_MTS_NOT_ENABLED 512U #define XRFDC_MTS_SYSREF_GATE_ERROR 2048U #define XRFDC_MTS_SYSREF_FREQ_NDONE 4096U #define XRFDC_MTS_BAD_REF_TILE 8192U /************************** Function Prototypes ******************************/ XRFdc_Config *XRFdc_LookupConfig(u16 DeviceId); u32 XRFdc_RegisterMetal(XRFdc *InstancePtr, u16 DeviceId, struct metal_device **DevicePtr); u32 XRFdc_CfgInitialize(XRFdc *InstancePtr, XRFdc_Config *ConfigPtr); u32 XRFdc_StartUp(XRFdc *InstancePtr, u32 Type, int Tile_Id); u32 XRFdc_Shutdown(XRFdc *InstancePtr, u32 Type, int Tile_Id); u32 XRFdc_Reset(XRFdc *InstancePtr, u32 Type, int Tile_Id); u32 XRFdc_GetIPStatus(XRFdc *InstancePtr, XRFdc_IPStatus *IPStatusPtr); u32 XRFdc_GetBlockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_BlockStatus *BlockStatusPtr); u32 XRFdc_SetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr); u32 XRFdc_GetMixerSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Mixer_Settings *MixerSettingsPtr); u32 XRFdc_SetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr); u32 XRFdc_GetQMCSettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_QMC_Settings *QMCSettingsPtr); u32 XRFdc_GetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr); u32 XRFdc_SetCoarseDelaySettings(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_CoarseDelay_Settings *CoarseDelaySettingsPtr); u32 XRFdc_GetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *InterpolationFactorPtr); u32 XRFdc_GetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr); u32 XRFdc_GetDecimationFactorObs(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecimationFactorPtr); u32 XRFdc_GetFabWrVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr); u32 XRFdc_GetFabWrVldWordsObs(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr); u32 XRFdc_GetFabRdVldWords(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr); u32 XRFdc_GetFabRdVldWordsObs(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *FabricDataRatePtr); u32 XRFdc_SetFabRdVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords); u32 XRFdc_SetFabRdVldWordsObs(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricRdVldWords); u32 XRFdc_SetFabWrVldWords(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 FabricWrVldWords); u32 XRFdc_GetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr); u32 XRFdc_SetThresholdSettings(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Threshold_Settings *ThresholdSettingsPtr); u32 XRFdc_SetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecoderMode); u32 XRFdc_UpdateEvent(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 Event); u32 XRFdc_GetDecoderMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *DecoderModePtr); u32 XRFdc_ResetNCOPhase(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id); void XRFdc_DumpRegs(XRFdc *InstancePtr, u32 Type, int Tile_Id); u32 XRFdc_MultiBand(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 DigitalDataPathMask, u32 MixerInOutDataType, u32 DataConverterMask); int XRFdc_GetConnectedIData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id); int XRFdc_GetConnectedQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id); u32 XRFdc_GetConnectedIQData(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, int *ConnectedIData, int *ConnectedQData); u32 XRFdc_IntrHandler(u32 Vector, void *XRFdcPtr); u32 XRFdc_IntrClr(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask); u32 XRFdc_GetIntrStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrStsPtr); u32 XRFdc_IntrDisable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask); u32 XRFdc_IntrEnable(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 IntrMask); u32 XRFdc_GetEnabledInterrupts(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *IntrMask); u32 XRFdc_SetThresholdClrMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate, u32 ClrMode); u32 XRFdc_ThresholdStickyClear(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 ThresholdToUpdate); void XRFdc_SetStatusHandler(XRFdc *InstancePtr, void *CallBackRef, XRFdc_StatusHandler FunctionPtr); u32 XRFdc_SetupFIFO(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable); u32 XRFdc_SetupFIFOObs(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable); u32 XRFdc_SetupFIFOBoth(XRFdc *InstancePtr, u32 Type, int Tile_Id, u8 Enable); u32 XRFdc_GetFIFOStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr); u32 XRFdc_GetFIFOStatusObs(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 *EnablePtr); u32 XRFdc_SetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 NyquistZone); u32 XRFdc_GetNyquistZone(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, u32 *NyquistZonePtr); u32 XRFdc_GetOutputCurr(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *OutputCurrPtr); u32 XRFdc_SetDecimationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor); u32 XRFdc_SetDecimationFactorObs(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 DecimationFactor); u32 XRFdc_SetInterpolationFactor(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 InterpolationFactor); u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 FabClkDiv); u32 XRFdc_SetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 CalibrationMode); u32 XRFdc_GetCalibrationMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u8 *CalibrationModePtr); u32 XRFdc_GetClockSource(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *ClockSourcePtr); u32 XRFdc_GetPLLLockStatus(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 *LockStatusPtr); u32 XRFdc_GetPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, XRFdc_PLL_Settings *PLLSettings); u32 XRFdc_DynamicPLLConfig(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u8 Source, double RefClkFreq, double SamplingRate); u32 XRFdc_SetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 Mode); u32 XRFdc_GetInvSincFIR(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u16 *ModePtr); u32 XRFdc_GetLinkCoupling(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr); u32 XRFdc_GetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u16 *FabClkDivPtr); u32 XRFdc_SetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode); u32 XRFdc_GetDither(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr); u32 XRFdc_SetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr); u32 XRFdc_GetClkDistribution(XRFdc *InstancePtr, XRFdc_Distribution_Settings *DistributionSettingsPtr); u32 XRFdc_SetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode); u32 XRFdc_GetDataPathMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr); u32 XRFdc_SetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Mode); u32 XRFdc_GetIMRPassMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *ModePtr); u32 XRFdc_SetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr); u32 XRFdc_GetSignalDetector(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Signal_Detector_Settings *SettingsPtr); u32 XRFdc_DisableCoefficientsOverride(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock); u32 XRFdc_SetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr); u32 XRFdc_GetCalCoefficients(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 CalibrationBlock, XRFdc_Calibration_Coefficients *CoeffPtr); u32 XRFdc_SetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr); u32 XRFdc_GetCalFreeze(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_Cal_Freeze_Settings *CalFreezePtr); u32 XRFdc_SetDACVOP(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 uACurrent); u32 XRFdc_SetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 Enable); u32 XRFdc_GetDACCompMode(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, u32 *EnabledPtr); u32 XRFdc_SetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr); u32 XRFdc_GetDSA(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id, XRFdc_DSA_Settings *SettingsPtr); u32 XRFdc_SetPwrMode(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Pwr_Mode_Settings *SettingsPtr); u32 XRFdc_GetPwrMode(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id, XRFdc_Pwr_Mode_Settings *SettingsPtr); u32 XRFdc_ResetInternalFIFOWidth(XRFdc *InstancePtr, u32 Type, u32 Tile_Id, u32 Block_Id); u32 XRFdc_ResetInternalFIFOWidthObs(XRFdc *InstancePtr, u32 Tile_Id, u32 Block_Id); void XRFdc_MultiConverter_Init(XRFdc_MultiConverter_Sync_Config *ConfigPtr, int *PLL_CodesPtr, int *T1_CodesPtr); u32 XRFdc_MultiConverter_Sync(XRFdc *InstancePtr, u32 Type, XRFdc_MultiConverter_Sync_Config *ConfigPtr); u32 XRFdc_MTS_Sysref_Config(XRFdc *InstancePtr, XRFdc_MultiConverter_Sync_Config *DACSyncConfigPtr, XRFdc_MultiConverter_Sync_Config *ADCSyncConfigPtr, u32 SysRefEnable);