Install the project... -- Install configuration: "RelWithDebInfo" -- Installing: /opt/xilinx/xrt/bin/unwrapped/xclbinutil -- Set runtime path of "/opt/xilinx/xrt/bin/unwrapped/xclbinutil" to "$ORIGIN/../lib:$ORIGIN/../..:$ORIGIN/../../lib" -- Installing: /opt/xilinx/xrt/bin/xclbinutil make[1]: Leaving directory '/root/xrt-git/build/xclbinutil_build/runtime_src/tools/xclbinutil' + mv /opt/xilinx/xrt/bin/unwrapped/xclbinutil /usr/local/bin/xclbinutil + rm -rf /opt/xilinx/xrt + echo Pynq-Z1 + cd /root + rm -rf xrt-git + rm /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/qemu.sh + '[' -e /home/pynq/PYNQ/sdbuild/packages/xrt/post.sh ']' + for p in $@ + '[' -n /home/pynq/PYNQ/sdbuild/../boards/Pynq-Z1/packages -a -e /home/pynq/PYNQ/sdbuild/../boards/Pynq-Z1/packages/pynq ']' + f=/home/pynq/PYNQ/sdbuild/packages/pynq + '[' -e /home/pynq/PYNQ/sdbuild/packages/pynq/pre.sh ']' + /home/pynq/PYNQ/sdbuild/packages/pynq/pre.sh /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1 + set -e + target=/home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1 +++ dirname /home/pynq/PYNQ/sdbuild/packages/pynq/pre.sh ++ cd /home/pynq/PYNQ/sdbuild/packages/pynq ++ pwd + script_dir=/home/pynq/PYNQ/sdbuild/packages/pynq + sudo mkdir -p /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/home/xilinx/pynq_git/boards [sudo] password for pynq: Sorry, try again. [sudo] password for pynq: + sudo mkdir -p /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/home/xilinx/pynq_git/dist + sudo cp /home/pynq/PYNQ/sdbuild/packages/pynq/pl_server.sh /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/usr/local/bin + sudo cp /home/pynq/PYNQ/sdbuild/packages/pynq/pl_server.service /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/lib/systemd/system + sudo cp /home/pynq/PYNQ/sdbuild/packages/pynq/pynq_hostname.sh /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/usr/local/bin + sudo cp /home/pynq/PYNQ/sdbuild/packages/pynq/boardname.sh /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/etc/profile.d ++ date +%Y_%m_%d ++ git rev-parse --short=7 --verify HEAD + echo 'Release 2022_09_01 59515a9' + '[' Pynq-Z1 '!=' Unknown ']' + cd /home/pynq/PYNQ/sdbuild/../boards/Pynq-Z1 + git tag + '[' 0 -eq 0 ']' ++ date +%Y_%m_%d ++ git rev-parse --short=7 --verify HEAD ++ git config --get remote.origin.url + echo 'Board 2022_09_01' 59515a9 https://github.com/Xilinx/PYNQ.git + '[' '!' -d /home/pynq/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z1 ']' + sudo cp -rf /home/pynq/PYNQ/sdbuild/build/PYNQ/REVISION /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/home/xilinx/REVISION + sudo cp -rf /home/pynq/PYNQ/sdbuild/build/PYNQ/REVISION /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/boot/REVISION + '[' -d /usr/local/share/fatfs_contents ']' + '[' -n '' ']' + '[' -n '' ']' + cd /home/pynq/PYNQ/sdbuild/build/PYNQ + ./build.sh ./build.sh Script for building default overlays, microblaze bsp's and binaries. building bitstream base.bit for Pynq-Z2 make[1]: Entering directory '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/base' rm -rf base *.jou *.log NA .Xil make[1]: Leaving directory '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/base' make[1]: Entering directory '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/base' vivado -mode batch -source build_ip.tcl -notrace ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source build_ip.tcl -notrace Building color_convert IP ****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source /home/pynq/xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace INFO: [HLS 200-10] Running '/home/pynq/xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls' INFO: [HLS 200-10] For user 'pynq' on host 'pynq-VirtualBox' (Linux_x86_64 version 5.4.0-124-generic) on Thu Sep 01 13:10:37 PDT 2022 INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS INFO: [HLS 200-10] In directory '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/ip/hls' Sourcing Tcl script 'color_convert/script.tcl' INFO: [HLS 200-1510] Running: open_project color_convert INFO: [HLS 200-10] Creating and opening project '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/ip/hls/color_convert'. INFO: [HLS 200-1510] Running: set_top color_convert INFO: [HLS 200-1510] Running: add_files color_convert/color_convert.cpp INFO: [HLS 200-10] Adding design file 'color_convert/color_convert.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb color_convert/color_convert_test.cpp INFO: [HLS 200-10] Adding test bench file 'color_convert/color_convert_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution1 INFO: [HLS 200-10] Creating and opening solution '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/ip/hls/color_convert/solution1'. INFO: [HLS 200-1505] Using default flow_target 'vivado' Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html INFO: [HLS 200-1510] Running: set_part xc7z020clg400-1 INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1' INFO: [HLS 200-1510] Running: create_clock -period 7 INFO: [SYN 201-201] Setting up clock 'default' with a period of 7ns. INFO: [HLS 200-1510] Running: csynth_design INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 205.856 MB. INFO: [HLS 200-10] Analyzing design file 'color_convert/color_convert.cpp' ... INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 4.64 seconds. CPU system time: 0.3 seconds. Elapsed time: 5.45 seconds; current allocated memory: 207.514 MB. INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target. INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_user_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:283:50) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_dest_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:286:25) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_id_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:285:67) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_user_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:285:36) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_dest_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:284:39) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_id_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:284:23) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_user_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:304:51) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_dest_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:307:26) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_id_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:306:68) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_user_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:306:37) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_dest_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:305:40) INFO: [HLS 214-131] Inlining function 'hls::axis, 1ul, 0ul, 0ul>::get_id_ptr()' into 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' (/home/pynq/xilinx/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:305:24) INFO: [HLS 214-131] Inlining function 'hls::stream, 1ul, 0ul, 0ul>, 0>::read(hls::axis, 1ul, 0ul, 0ul>&)' into 'color_convert(hls::stream, 1ul, 0ul, 0ul>, 0>&, hls::stream, 1ul, 0ul, 0ul>, 0>&, coeffs, coeffs, coeffs, coeffs)' (color_convert/color_convert.cpp:24:15) INFO: [HLS 214-131] Inlining function 'hls::stream, 1ul, 0ul, 0ul>, 0>::write(hls::axis, 1ul, 0ul, 0ul> const&)' into 'color_convert(hls::stream, 1ul, 0ul, 0ul>, 0>&, hls::stream, 1ul, 0ul, 0ul>, 0>&, coeffs, coeffs, coeffs, coeffs)' (color_convert/color_convert.cpp:38:16) INFO: [HLS 214-210] Disaggregating variable '' INFO: [HLS 214-210] Disaggregating variable '' INFO: [HLS 214-210] Disaggregating variable '' INFO: [HLS 214-210] Disaggregating variable '' INFO: [HLS 214-178] Inlining function 'channels::channels(ap_uint<24>)' into 'color_convert(hls::stream, 1ul, 0ul, 0ul>, 0>&, hls::stream, 1ul, 0ul, 0ul>, 0>&, coeffs, coeffs, coeffs, coeffs)' (color_convert/color_convert.cpp:8:0) INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.42 seconds. CPU system time: 0.18 seconds. Elapsed time: 3.85 seconds; current allocated memory: 208.721 MB. INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 208.723 MB. INFO: [HLS 200-10] Starting code transformations ... INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.15 seconds. CPU system time: 0 seconds. Elapsed time: 0.2 seconds; current allocated memory: 218.133 MB. INFO: [HLS 200-10] Checking synthesizability ... INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.29 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.31 seconds; current allocated memory: 230.641 MB. INFO: [XFORM 203-401] Performing if-conversion on hyperblock to (color_convert/color_convert.cpp:40:1) in function 'color_convert'... converting 19 basic blocks. INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.84 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.87 seconds; current allocated memory: 265.109 MB. INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.62 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.64 seconds; current allocated memory: 264.368 MB. INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'color_convert' ... INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'color_convert' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'color_convert'. INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 6, function 'color_convert' INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.23 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.24 seconds; current allocated memory: 265.161 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Finished Binding: CPU user time: 0.19 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.23 seconds; current allocated memory: 266.139 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'color_convert' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_in_24_V_data_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_in_24_V_keep_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_in_24_V_strb_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_in_24_V_user_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_in_24_V_last_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_out_24_V_data_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_out_24_V_keep_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_out_24_V_strb_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_out_24_V_user_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/stream_out_24_V_last_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c1_0' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c1_1' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c1_2' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c2_0' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c2_1' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c2_2' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c3_0' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c3_1' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/c3_2' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/bias_0' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/bias_1' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'color_convert/bias_2' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on function 'color_convert' to 'ap_ctrl_none'. INFO: [RTGEN 206-100] Bundling port 'c1_0', 'c1_1', 'c1_2', 'c2_0', 'c2_1', 'c2_2', 'c3_0', 'c3_1', 'c3_2', 'bias_0', 'bias_1' and 'bias_2' to AXI-Lite port control. INFO: [RTGEN 206-100] Generating core module 'mul_10s_8ns_18_1_1': 9 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'color_convert'. INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.43 seconds. CPU system time: 0 seconds. Elapsed time: 0.43 seconds; current allocated memory: 267.719 MB. INFO: [RTMG 210-282] Generating pipelined core: 'color_convert_mul_10s_8ns_18_1_1_Multiplier_0' INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 2.55 seconds. CPU system time: 0.05 seconds. Elapsed time: 2.63 seconds; current allocated memory: 278.506 MB. INFO: [VHDL 208-304] Generating VHDL RTL for color_convert. INFO: [VLOG 209-307] Generating Verilog RTL for color_convert. INFO: [HLS 200-789] **** Estimated Fmax: 221.24 MHz INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 13.54 seconds. CPU system time: 0.6 seconds. Elapsed time: 15.05 seconds; current allocated memory: 278.856 MB. INFO: [HLS 200-1510] Running: export_design -format ip_catalog -description Color conversion for 24-bit AXI video stream -display_name Color Convert INFO: [IMPL 213-8] Exporting RTL as a Vivado IP. ****** Vivado v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source run_ippack.tcl -notrace bad lexical cast: source type value could not be interpreted as target while executing "rdi::set_property core_revision 2209011310 {component component_1}" invoked from within "set_property core_revision $Revision $core" (file "run_ippack.tcl" line 937) INFO: [Common 17-206] Exiting Vivado at Thu Sep 1 13:11:09 2022... ERROR: [IMPL 213-28] Failed to generate IP. INFO: [HLS 200-111] Finished Command export_design CPU user time: 12.96 seconds. CPU system time: 0.98 seconds. Elapsed time: 17.57 seconds; current allocated memory: 282.265 MB. command 'ap_source' returned error code while executing "source color_convert/script.tcl" ("uplevel" body line 1) invoked from within "uplevel \#0 [list source $arg] " INFO: [HLS 200-112] Total CPU user time: 29.31 seconds. Total CPU system time: 2.03 seconds. Total elapsed time: 36.13 seconds; peak allocated memory: 278.506 MB. INFO: [Common 17-206] Exiting vitis_hls at Thu Sep 1 13:11:13 2022... child process exited abnormally INFO: [Common 17-206] Exiting Vivado at Thu Sep 1 13:11:13 2022... makefile:10: recipe for target 'hls_ip' failed make[1]: *** [hls_ip] Error 1 make[1]: Leaving directory '/home/pynq/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/base' + unmount_special + for fs in $fss + sudo umount -l /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/proc + for fs in $fss + sudo umount -l /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/run + for fs in $fss + sudo umount -l /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/dev + sudo umount -l /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/ccache + rmdir /home/pynq/PYNQ/sdbuild/build/focal.Pynq-Z1/ccache Makefile:343: recipe for target '/home/pynq/PYNQ/sdbuild/build/Pynq-Z1.tar.gz' failed make: *** [/home/pynq/PYNQ/sdbuild/build/Pynq-Z1.tar.gz] Error 2