`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 09/10/2021 06:48:43 PM
// Design Name: 
// Module Name: core
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module core #(parameter H = 360, W=640 ,DATA_WIDTH=8)(
input    axi_clk,
    input    axi_reset_n,
    //AXI4-S slave i/f
    input    s_axis_valid,
    input [DATA_WIDTH-1:0] s_axis_data,
    output reg s_axis_ready,
    //AXI4-S master i/f
    output reg  m_axis_valid,
    output reg [DATA_WIDTH-1:0] m_axis_data,
    input    m_axis_ready,
    output  reg  m_axis_tlast);
reg [DATA_WIDTH-1:0] InMem[0:W-1];
reg [10:0] wrPntr,rdPntr;
// Keeps the slave axis wake untill on line of image is read 
always @(posedge axi_clk)
    if(wrPntr < W-1)
        begin
         s_axis_ready <= 1;
        
        end
    else
         begin
          s_axis_ready <= 0;
      
         end

// Keeps the master axis data unvalid untill total line buffer is read 
always @(posedge axi_clk)
    if(rdPntr < W-1)
        begin
        m_axis_valid <= 0;
        m_axis_tlast <= 1;
        end
    else
    begin
        m_axis_valid <= 1;
        m_axis_tlast <= 0;
    end
// Read from PS and writes to Line Buffer
always @(posedge axi_clk)
    if(s_axis_valid & s_axis_ready)
        begin
            InMem[rdPntr] <= s_axis_data;
            rdPntr <= rdPntr + 1;
        end
    else
            rdPntr <= 0;

// Read from Line Buffer and writes to PS
  always @(posedge axi_clk)
    if(m_axis_valid & m_axis_ready)
        begin
            m_axis_data <= InMem[wrPntr];
            wrPntr <= wrPntr + 1;
        end
    else begin
            wrPntr <= 0;
            m_axis_data <= 0;
            end
       
endmodule