/opt/qemu/bin/qemu-arm-static -version | fgrep 4.0.0
qemu-arm version 4.0.0
vivado -version | fgrep 2020.1
Vivado v2020.1 (64-bit)
vitis -version | fgrep 2020.1
****** Vitis v2020.1 (64-bit)
which petalinux-config
/home/pynq/Documents/petalinux2020.1/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/home/pynq/Xilinx//Vitis/2020.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/home/pynq/Documents/petalinux2020.1/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
which python | fgrep /usr/bin/python
/usr/bin/python
sudo -n mount > /dev/null
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_env.sh
Pass: Current OS is supported.
Checking system for installed bc
gperf
bison
flex
texi2html
texinfo
help2man
gawk
libtool
libtool-bin
build-essential
automake
libncurses5-dev
libglib2.0-dev
device-tree-compiler
qemu-user-static
binfmt-support
multistrap
git
lib32z1
lib32ncurses5
libbz2-1.0
lib32stdc++6
libssl-dev
kpartx
zerofree
u-boot-tools
rpm2cpio
libsdl1.2-dev
rsync
python3-pip
gcc-multilib
libidn11
curl
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_mounts.sh
mkdir -p /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1
cp /home/pynq/Documents/PYNQ/sdbuild/boot/image_arm.its /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/image.its
rm -rf /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
mkdir -p /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
BSP= BSP_BUILD=/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz1-2020.1 /home/pynq/Documents/PYNQ/sdbuild/scripts/create_bsp.sh /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1 zynq
make[1]: Entering directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
vivado -mode batch -source pynqz1.tcl -notrace

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pynqz1.tcl -notrace
INFO: [BD::TCL 103-2003] Currently there is no design <pynqz1> in project, so creating one...
Wrote  : </home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> 
INFO: [BD::TCL 103-2004] Making design <pynqz1> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "pynqz1".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1  .
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
Wrote  : </home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> 
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 12:52:59 2021...
vivado -mode batch -source build_bitstream.tcl -notrace

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source build_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/pynq/Xilinx/Vivado/2020.1/data/ip'.
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ps7
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk1
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk3
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <pynqz1> from BD file <./pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd>
INFO: [BD 41-1662] The design 'pynqz1.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v
INFO: [BD 41-1662] The design 'pynqz1.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1.hwh
Generated Block Design Tcl file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1_bd.tcl
Generated Hardware Definition File /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.hwdef
[Thu Jun 10 12:53:32 2021] Launched pynqz1_rst_ps7_0_fclk3_0_synth_1, pynqz1_rst_ps7_0_fclk2_0_synth_1, pynqz1_rst_ps7_0_fclk1_0_synth_1, pynqz1_rst_ps7_0_fclk0_0_synth_1, pynqz1_ps7_0_synth_1, synth_1...
Run output will be captured here:
pynqz1_rst_ps7_0_fclk3_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk3_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk2_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk2_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk1_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk1_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk0_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk0_0_synth_1/runme.log
pynqz1_ps7_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_ps7_0_synth_1/runme.log
synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/synth_1/runme.log
[Thu Jun 10 12:53:32 2021] Launched impl_1...
Run output will be captured here: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2253.047 ; gain = 40.016 ; free physical = 25512 ; free virtual = 32026
[Thu Jun 10 12:53:32 2021] Waiting for impl_1 to finish...

*** Running vivado
    with args -log pynqz1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pynqz1_wrapper.tcl -notrace


****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pynqz1_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/pynq/Xilinx/Vivado/2020.1/data/ip'.
Command: link_design -top pynqz1_wrapper -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.dcp' for cell 'pynqz1_i/ps7'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk0'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk1'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk2'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk3'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2149.199 ; gain = 0.000 ; free physical = 24874 ; free virtual = 31391
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2149.199 ; gain = 0.000 ; free physical = 24775 ; free virtual = 31292
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2149.199 ; gain = 0.094 ; free physical = 24775 ; free virtual = 31292
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2157.109 ; gain = 7.910 ; free physical = 24769 ; free virtual = 31286

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1ecd42c96

Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2480.078 ; gain = 322.969 ; free physical = 24392 ; free virtual = 30909

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1f53c997a

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24228 ; free virtual = 30746
INFO: [Opt 31-389] Phase Retarget created 8 cells and removed 36 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1f53c997a

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24228 ; free virtual = 30746
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 239e66fde

Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24228 ; free virtual = 30746
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 349 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 239e66fde

Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24228 ; free virtual = 30746
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 239e66fde

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 239e66fde

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               8  |              36  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |             349  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745
Ending Logic Optimization Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745
Ending Netlist Obfuscation Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24227 ; free virtual = 30745
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2642.047 ; gain = 492.848 ; free physical = 24227 ; free virtual = 30745
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2642.047 ; gain = 0.000 ; free physical = 24222 ; free virtual = 30743
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx
Command: report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24213 ; free virtual = 30732
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1650a874b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24213 ; free virtual = 30732
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24213 ; free virtual = 30732

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1650a874b

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30727

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24209 ; free virtual = 30728

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30727
Phase 1 Placer Initialization | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30727

Phase 2 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30727
Phase 2 Final Placement Cleanup | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30727
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 1650a874b

Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24209 ; free virtual = 30728
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30731
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file pynqz1_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24199 ; free virtual = 30719
INFO: [runtcl-4] Executing : report_utilization -file pynqz1_wrapper_utilization_placed.rpt -pb pynqz1_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file pynqz1_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24208 ; free virtual = 30728
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2706.078 ; gain = 0.000 ; free physical = 24206 ; free virtual = 30729
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 98566580 ConstDB: 0 ShapeSum: ccb421cb RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2784.992 ; gain = 78.914 ; free physical = 24067 ; free virtual = 30588
Post Restoration Checksum: NetGraph: af787cf2 NumContArr: 6a93504a Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2784.992 ; gain = 78.914 ; free physical = 24064 ; free virtual = 30584

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2788.992 ; gain = 82.914 ; free physical = 24060 ; free virtual = 30580

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2788.992 ; gain = 82.914 ; free physical = 24060 ; free virtual = 30580
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: cbf8d822

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2795.047 ; gain = 88.969 ; free physical = 24057 ; free virtual = 30578
Phase 2 Router Initialization | Checksum: cbf8d822

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2795.047 ; gain = 88.969 ; free physical = 24057 ; free virtual = 30578

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 130
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 130
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577
Phase 4 Rip-up And Reroute | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577
Phase 5 Delay and Skew Optimization | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577
Phase 6.1 Hold Fix Iter | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577
Phase 6 Post Hold Fix | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24056 ; free virtual = 30577

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24054 ; free virtual = 30575

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24054 ; free virtual = 30575

Phase 10 Post Router Timing
Phase 10 Post Router Timing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2798.754 ; gain = 92.676 ; free physical = 24055 ; free virtual = 30576
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2816.598 ; gain = 110.520 ; free physical = 24060 ; free virtual = 30580

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2816.598 ; gain = 110.520 ; free physical = 24059 ; free virtual = 30580
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2816.598 ; gain = 0.000 ; free physical = 24056 ; free virtual = 30580
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx
Command: report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx
Command: report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
71 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file pynqz1_wrapper_route_status.rpt -pb pynqz1_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pynqz1_wrapper_timing_summary_routed.rpt -pb pynqz1_wrapper_timing_summary_routed.pb -rpx pynqz1_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_incremental_reuse -file pynqz1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file pynqz1_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pynqz1_wrapper_bus_skew_routed.rpt -pb pynqz1_wrapper_bus_skew_routed.pb -rpx pynqz1_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
Command: write_bitstream -force pynqz1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./pynqz1_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Jun 10 12:58:28 2021. For additional details about this file, please refer to the WebTalk help file at /home/pynq/Xilinx/Vivado/2020.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 3165.738 ; gain = 346.172 ; free physical = 24034 ; free virtual = 30559
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 12:58:28 2021...
[Thu Jun 10 12:58:28 2021] impl_1 finished
wait_on_run: Time (s): cpu = 00:03:55 ; elapsed = 00:04:56 . Memory (MB): peak = 2253.047 ; gain = 0.000 ; free physical = 25504 ; free virtual = 32029
INFO: [Vivado 12-4895] Creating Hardware Platform: ./pynqz1.xsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Hsi 55-2053] elapsed time for repository (/home/pynq/Xilinx/Vivado/2020.1/data/embeddedsw) loading 0 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2261.062 ; gain = 8.016 ; free physical = 25477 ; free virtual = 32014
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1.xsa
write_hw_platform: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2261.062 ; gain = 8.016 ; free physical = 25482 ; free virtual = 32010
INFO: [Vivado 12-6074] Validating Hardware Platform: './pynqz1.xsa'
INFO: [Vivado 12-8115] Found XML metadata file: xsa.xml
INFO: [Vivado 12-6078] Validating platform properties...
INFO: [Vivado 12-6079] Validating unified platform...
INFO: [Vivado 12-6073] Validating 'pre_synth' platform state...
INFO: [Vivado 12-6077] Validating platform files...
INFO: [Vivado 12-6067] Found file 'pynqz1.bit' of type 'FULL_BIT' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'pynqz1.hpfm' of type 'HPFM' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/rebuild.tcl' of type 'REBUILD_TCL' in the Hardware Platform.
INFO: [Vivado 12-6066] Finished running validate_dsa for file: './pynqz1.xsa'
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 12:58:42 2021...

Built pynqz1 successfully!
(B
make[1]: Leaving directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
INFO: Create project: xilinx-pynqz1-2020.1
INFO: New project successfully created in /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1
INFO: sourcing build tools
INFO: Getting hardware description...
INFO: Rename pynqz1.xsa to system.xsa
[INFO] generating Kconfig for project
INFO: [Hsi 55-2053] elapsed time for repository (/home/pynq/Documents/petalinux2020.1/tools/xsct/data/embeddedsw) loading 0 seconds
[INFO] silentconfig project
env: ‘conf’: No such file or directory
Makefile:338: recipe for target '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1.bsp' failed
/opt/qemu/bin/qemu-arm-static -version | fgrep 4.0.0
qemu-arm version 4.0.0
vivado -version | fgrep 2020.1
Vivado v2020.1 (64-bit)
vitis -version | fgrep 2020.1
****** Vitis v2020.1 (64-bit)
which petalinux-config
/home/pynq/Documents/petalinux2020.1/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/home/pynq/Xilinx//Vitis/2020.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/home/pynq/Documents/petalinux2020.1/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
which python | fgrep /usr/bin/python
/usr/bin/python
sudo -n mount > /dev/null
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_env.sh
Pass: Current OS is supported.
Checking system for installed bc
gperf
bison
flex
texi2html
texinfo
help2man
gawk
libtool
libtool-bin
build-essential
automake
libncurses5-dev
libglib2.0-dev
device-tree-compiler
qemu-user-static
binfmt-support
multistrap
git
lib32z1
lib32ncurses5
libbz2-1.0
lib32stdc++6
libssl-dev
kpartx
zerofree
u-boot-tools
rpm2cpio
libsdl1.2-dev
rsync
python3-pip
gcc-multilib
libidn11
curl
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_mounts.sh
BSP= BSP_BUILD=/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz1-2020.1 /home/pynq/Documents/PYNQ/sdbuild/scripts/create_bsp.sh /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1 zynq
+ set -e
+ board=/home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1
+ template=zynq
+ '[' -n '' ']'
+ cp -rf /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/hardware_project /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/meta-user /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
+ cd /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project
+ '[' -e makefile ']'
+ make
make[1]: Entering directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
vivado -mode batch -source pynqz1.tcl -notrace

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pynqz1.tcl -notrace
ERROR: [Common 17-53] User Exception: Project already exists on disk, please use '-force' option to overwrite: 
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.xpr
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.cache
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.hw
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.ip_user_files
     /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.hbs
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 12:59:56 2021...
makefile:10: recipe for target 'block_design' failed
make[1]: *** [block_design] Error 1
make[1]: Leaving directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
Makefile:338: recipe for target '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1.bsp' failed
make: *** [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1.bsp] Error 2
/opt/qemu/bin/qemu-arm-static -version | fgrep 4.0.0
qemu-arm version 4.0.0
vivado -version | fgrep 2020.1
Vivado v2020.1 (64-bit)
vitis -version | fgrep 2020.1
****** Vitis v2020.1 (64-bit)
which petalinux-config
/home/pynq/Documents/petalinux2020.1/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/home/pynq/Xilinx//Vitis/2020.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/home/pynq/Documents/petalinux2020.1/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
which python | fgrep /usr/bin/python
/usr/bin/python
sudo -n mount > /dev/null
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_env.sh
Pass: Current OS is supported.
Checking system for installed bc
gperf
bison
flex
texi2html
texinfo
help2man
gawk
libtool
libtool-bin
build-essential
automake
libncurses5-dev
libglib2.0-dev
device-tree-compiler
qemu-user-static
binfmt-support
multistrap
git
lib32z1
lib32ncurses5
libbz2-1.0
lib32stdc++6
libssl-dev
kpartx
zerofree
u-boot-tools
rpm2cpio
libsdl1.2-dev
rsync
python3-pip
gcc-multilib
libidn11
curl
bash /home/pynq/Documents/PYNQ/sdbuild/scripts/check_mounts.sh
mkdir -p /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1
cp /home/pynq/Documents/PYNQ/sdbuild/boot/image_arm.its /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/image.its
rm -rf /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
mkdir -p /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
BSP= BSP_BUILD=/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz1-2020.1 /home/pynq/Documents/PYNQ/sdbuild/scripts/create_bsp.sh /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1 zynq
+ set -e
+ board=/home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1
+ template=zynq
+ '[' -n '' ']'
+ cp -rf /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/hardware_project /home/pynq/Documents/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/meta-user /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
+ cd /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project
+ '[' -e makefile ']'
+ make
make[1]: Entering directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
vivado -mode batch -source pynqz1.tcl -notrace

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pynqz1.tcl -notrace
INFO: [BD::TCL 103-2003] Currently there is no design <pynqz1> in project, so creating one...
Wrote  : </home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> 
INFO: [BD::TCL 103-2004] Making design <pynqz1> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "pynqz1".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1  .
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
Wrote  : </home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> 
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 13:00:25 2021...
vivado -mode batch -source build_bitstream.tcl -notrace

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source build_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/pynq/Xilinx/Vivado/2020.1/data/ip'.
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ps7
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP2_wr_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_rd_socket' specified in the portmap, is not found on the block! 
WARNING: [BD 41-176] The physical port 'S_AXI_GP3_wr_socket' specified in the portmap, is not found on the block! 
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk1
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk3
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <pynqz1> from BD file <./pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd>
INFO: [BD 41-1662] The design 'pynqz1.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v
INFO: [BD 41-1662] The design 'pynqz1.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v
VHDL Output written to : /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1.hwh
Generated Block Design Tcl file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1_bd.tcl
Generated Hardware Definition File /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.hwdef
[Thu Jun 10 13:00:58 2021] Launched pynqz1_rst_ps7_0_fclk3_0_synth_1, pynqz1_rst_ps7_0_fclk2_0_synth_1, pynqz1_rst_ps7_0_fclk1_0_synth_1, pynqz1_rst_ps7_0_fclk0_0_synth_1, pynqz1_ps7_0_synth_1, synth_1...
Run output will be captured here:
pynqz1_rst_ps7_0_fclk3_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk3_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk2_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk2_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk1_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk1_0_synth_1/runme.log
pynqz1_rst_ps7_0_fclk0_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_rst_ps7_0_fclk0_0_synth_1/runme.log
pynqz1_ps7_0_synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_ps7_0_synth_1/runme.log
synth_1: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/synth_1/runme.log
[Thu Jun 10 13:00:58 2021] Launched impl_1...
Run output will be captured here: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2251.109 ; gain = 40.016 ; free physical = 25511 ; free virtual = 32025
[Thu Jun 10 13:00:58 2021] Waiting for impl_1 to finish...

*** Running vivado
    with args -log pynqz1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pynqz1_wrapper.tcl -notrace


****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source pynqz1_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/pynq/Xilinx/Vivado/2020.1/data/ip'.
Command: link_design -top pynqz1_wrapper -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.dcp' for cell 'pynqz1_i/ps7'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk0'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk1'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk2'
INFO: [Project 1-454] Reading design checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.dcp' for cell 'pynqz1_i/rst_ps7_0_fclk3'
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2149.203 ; gain = 0.000 ; free physical = 23650 ; free virtual = 30939
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk0_0/pynqz1_rst_ps7_0_fclk0_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk0/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk1_0/pynqz1_rst_ps7_0_fclk1_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk1/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk2_0/pynqz1_rst_ps7_0_fclk2_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk2/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0_board.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
Finished Parsing XDC File [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_rst_ps7_0_fclk3_0/pynqz1_rst_ps7_0_fclk3_0.xdc] for cell 'pynqz1_i/rst_ps7_0_fclk3/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2149.203 ; gain = 0.000 ; free physical = 23515 ; free virtual = 30841
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2149.203 ; gain = 0.094 ; free physical = 23515 ; free virtual = 30841
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2157.113 ; gain = 7.910 ; free physical = 23508 ; free virtual = 30834

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1ecd42c96

Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2476.113 ; gain = 319.000 ; free physical = 23127 ; free virtual = 30457

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1f53c997a

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22963 ; free virtual = 30293
INFO: [Opt 31-389] Phase Retarget created 8 cells and removed 36 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1f53c997a

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22963 ; free virtual = 30293
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 239e66fde

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22963 ; free virtual = 30293
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 349 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 239e66fde

Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22963 ; free virtual = 30293
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 239e66fde

Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30293
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 239e66fde

Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30293
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               8  |              36  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |             349  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30293
Ending Logic Optimization Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30293

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30292

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30292

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30292
Ending Netlist Obfuscation Task | Checksum: 1ab910b8a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22962 ; free virtual = 30292
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2641.051 ; gain = 491.848 ; free physical = 22962 ; free virtual = 30292
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2641.051 ; gain = 0.000 ; free physical = 22957 ; free virtual = 30291
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx
Command: report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22947 ; free virtual = 30280
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1650a874b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22947 ; free virtual = 30280
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22947 ; free virtual = 30280

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1650a874b

Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30275

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22943 ; free virtual = 30275

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30275
Phase 1 Placer Initialization | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30275

Phase 2 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30275
Phase 2 Final Placement Cleanup | Checksum: 1b350f07d

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30275
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 1650a874b

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22943 ; free virtual = 30276
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30278
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file pynqz1_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22933 ; free virtual = 30267
INFO: [runtcl-4] Executing : report_utilization -file pynqz1_wrapper_utilization_placed.rpt -pb pynqz1_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file pynqz1_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22942 ; free virtual = 30276
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2705.082 ; gain = 0.000 ; free physical = 22940 ; free virtual = 30277
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command route_design
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
Checksum: PlaceDB: 98566580 ConstDB: 0 ShapeSum: ccb421cb RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2783.965 ; gain = 78.883 ; free physical = 22790 ; free virtual = 30136
Post Restoration Checksum: NetGraph: af787cf2 NumContArr: 6a93504a Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2783.965 ; gain = 78.883 ; free physical = 22786 ; free virtual = 30132

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2787.965 ; gain = 82.883 ; free physical = 22782 ; free virtual = 30128

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 11a0bcd3c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2787.965 ; gain = 82.883 ; free physical = 22782 ; free virtual = 30128
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: cbf8d822

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2794.020 ; gain = 88.938 ; free physical = 22778 ; free virtual = 30126
Phase 2 Router Initialization | Checksum: cbf8d822

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2794.020 ; gain = 88.938 ; free physical = 22777 ; free virtual = 30126

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 130
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 130
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125
Phase 4 Rip-up And Reroute | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125
Phase 5 Delay and Skew Optimization | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125
Phase 6.1 Hold Fix Iter | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125
Phase 6 Post Hold Fix | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22775 ; free virtual = 30125

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22773 ; free virtual = 30124

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22773 ; free virtual = 30124

Phase 10 Post Router Timing
Phase 10 Post Router Timing | Checksum: 3de5fc8d

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.727 ; gain = 92.645 ; free physical = 22774 ; free virtual = 30124
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2816.570 ; gain = 111.488 ; free physical = 22778 ; free virtual = 30129

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2816.570 ; gain = 111.488 ; free physical = 22778 ; free virtual = 30129
INFO: [Common 17-600] The following parameters have non-default value.
general.maxThreads
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2816.570 ; gain = 0.000 ; free physical = 22773 ; free virtual = 30128
INFO: [Common 17-1381] The checkpoint '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx
Command: report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Coretcl 2-168] The results of DRC are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx
Command: report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
71 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file pynqz1_wrapper_route_status.rpt -pb pynqz1_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pynqz1_wrapper_timing_summary_routed.rpt -pb pynqz1_wrapper_timing_summary_routed.pb -rpx pynqz1_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [runtcl-4] Executing : report_incremental_reuse -file pynqz1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file pynqz1_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pynqz1_wrapper_bus_skew_routed.rpt -pb pynqz1_wrapper_bus_skew_routed.pb -rpx pynqz1_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
Command: write_bitstream -force pynqz1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./pynqz1_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Jun 10 13:06:35 2021. For additional details about this file, please refer to the WebTalk help file at /home/pynq/Xilinx/Vivado/2020.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 3163.742 ; gain = 344.203 ; free physical = 22590 ; free virtual = 30103
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 13:06:35 2021...
[Thu Jun 10 13:06:36 2021] impl_1 finished
wait_on_run: Time (s): cpu = 00:03:57 ; elapsed = 00:05:37 . Memory (MB): peak = 2251.109 ; gain = 0.000 ; free physical = 24048 ; free virtual = 31571
INFO: [Vivado 12-4895] Creating Hardware Platform: ./pynqz1.xsa ...
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Hsi 55-2053] elapsed time for repository (/home/pynq/Xilinx/Vivado/2020.1/data/embeddedsw) loading 0 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 2259.125 ; gain = 8.016 ; free physical = 23567 ; free virtual = 31542
INFO: [Vivado 12-4896] Successfully created Hardware Platform: /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1.xsa
write_hw_platform: Time (s): cpu = 00:00:14 ; elapsed = 00:00:23 . Memory (MB): peak = 2259.125 ; gain = 8.016 ; free physical = 23501 ; free virtual = 31536
INFO: [Vivado 12-6074] Validating Hardware Platform: './pynqz1.xsa'
INFO: [Vivado 12-8115] Found XML metadata file: xsa.xml
INFO: [Vivado 12-6078] Validating platform properties...
INFO: [Vivado 12-6079] Validating unified platform...
INFO: [Vivado 12-6073] Validating 'pre_synth' platform state...
INFO: [Vivado 12-6077] Validating platform files...
INFO: [Vivado 12-6067] Found file 'pynqz1.bit' of type 'FULL_BIT' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'pynqz1.hpfm' of type 'HPFM' in the Hardware Platform.
INFO: [Vivado 12-6067] Found file 'prj/rebuild.tcl' of type 'REBUILD_TCL' in the Hardware Platform.
INFO: [Vivado 12-6066] Finished running validate_dsa for file: './pynqz1.xsa'
INFO: [Common 17-206] Exiting Vivado at Thu Jun 10 13:06:59 2021...

Built pynqz1 successfully!
(B
make[1]: Leaving directory '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project'
+ cd /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp
+ petalinux-create --type project --template zynq --name xilinx-pynqz1-2020.1
INFO: Create project: xilinx-pynqz1-2020.1
INFO: New project successfully created in /home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1
+ cd xilinx-pynqz1-2020.1
+ petalinux-config --get-hw-description=/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project --silentconfig -v
INFO: sourcing build tools
INFO: Getting hardware description...
INFO: Rename pynqz1.xsa to system.xsa
[INFO] generating Kconfig for project
INFO: [Hsi 55-2053] elapsed time for repository (/home/pynq/Documents/petalinux2020.1/tools/xsct/data/embeddedsw) loading 0 seconds
[INFO] silentconfig project
env: ‘conf’: No such file or directory
ERROR: Failed to silentconfig project component 
ERROR: Failed to config project.
ERROR: Get hw description Failed!.
Makefile:338: recipe for target '/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1.bsp' failed
make: *** [/home/pynq/Documents/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2020.1.bsp] Error 255