start_gui cd /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base source ./build_ip.tcl # set current_dir [pwd] # cd ../../ip/hls/ # set ip {color_convert_2 pixel_pack_2 pixel_unpack_2} # foreach item $ip { # if {[catch { glob -directory ${item}/solution1/impl/ip/ *.zip} zip_file]} { # # Build IP only if a packaged IP does not exist # puts "Building $item IP" # exec vivado_hls -f $item/script.tcl # } else { # # Skip IP when a packaged IP exists in ip directory # puts "Skipping building $item" # } # unset zip_file # # Testing the built IP # puts "Checking $item" # set fd [open ${item}/solution1/syn/report/${item}_csynth.rpt r] # set timing_flag 0 # set latency_flag 0 # while { [gets $fd line] >= 0 } { # # Check whether the timing has been met # if [string match {+ Timing: } $line] { # set timing_flag 1 # set latency_flag 0 # continue # } # if {$timing_flag == 1} { # if [regexp {[0-9]+} $line] { # set period [regexp -all -inline {[0-9]*\.[0-9]*} $line] # lassign $period target estimated uncertainty # if {$target < $estimated} { # puts "ERROR: Estimated clock period $estimated > target $target." # puts "ERROR: Revise $item to be compatible with Vivado_HLS." # exit 1 # } # } # } # # Check whether the II has been met # if [string match {+ Latency: } $line] { # set timing_flag 0 # set latency_flag 1 # continue # } # if {$latency_flag == 1} { # if [regexp {[0-9]+} $line] { # set interval [regexp -all -inline {[0-9]*\.*[0-9]*} $line] # lassign $interval lc_min lc_max la_min la_max achieved target # if {$achieved != $target} { # puts "ERROR: Achieved II $achieved != target $target." # puts "ERROR: Revise $item to be compatible with Vivado_HLS." # exit 1 # } # } # } # # Testing ends # if [string match {== Utilization Estimates} $line] { # unset timing_flag latency_flag period interval # break # } # } # unset fd # } Building color_convert_2 IP Checking color_convert_2 Building pixel_pack_2 IP Checking pixel_pack_2 Building pixel_unpack_2 IP Checking pixel_unpack_2 # cd $current_dir # puts "HLS IP builds complete" HLS IP builds complete source ./base.tcl # namespace eval _tcl { # proc get_script_folder {} { # set script_path [file normalize [info script]] # set script_folder [file dirname $script_path] # return $script_folder # } # } # variable script_folder # set script_folder [_tcl::get_script_folder] # set scripts_vivado_version 2020.1 # set current_vivado_version [version -short] # if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # puts "" # catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} # # return 1 # } # set overlay_name base # set list_projs [get_projects -quiet] # if { $list_projs eq "" } { # create_project ${overlay_name} ${overlay_name} -part xczu7ev-ffvc1156-2-e # set_property BOARD_PART xilinx.com:zcu104:part0:1.0 [current_project] # } INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hughesyang/tools/Vivado/2020.1/data/ip'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 7158.965 ; gain = 40.039 ; free physical = 11556 ; free virtual = 17914 # set_property ip_repo_paths ../../ip [current_project] # update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hughesyang/Downloads/PYNQ-master/boards/ip'. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. # variable design_name # set design_name base # set errMsg "" # set nRet 0 # set cur_design [current_bd_design -quiet] # set list_cells [get_bd_cells -quiet] # if { ${design_name} eq "" } { # # USE CASES: # # 1) Design_name not set # # set errMsg "Please set the variable to a non-empty value." # set nRet 1 # # } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { # # USE CASES: # # 2): Current design opened AND is empty AND names same. # # 3): Current design opened AND is empty AND names diff; design_name NOT in project. # # 4): Current design opened AND is empty AND names diff; design_name exists in project. # # if { $cur_design ne $design_name } { # common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." # set design_name [get_property NAME $cur_design] # } # common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." # # } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # # USE CASES: # # 5) Current design opened AND has components AND same names. # # set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." # set nRet 1 # } elseif { [get_files -quiet ${design_name}.bd] ne "" } { # # USE CASES: # # 6) Current opened design, has components, but diff names, design_name exists in project. # # 7) No opened design, design_name exists in project. # # set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." # set nRet 2 # # } else { # # USE CASES: # # 8) No opened design, design_name not in project. # # 9) Current opened design, has components, but diff names, design_name not in project. # # common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." # # create_bd_design $design_name # # common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." # current_bd_design $design_name # # } INFO: [BD::TCL 103-2003] Currently there is no design in project, so creating one... Wrote : create_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 7188.891 ; gain = 27.711 ; free physical = 11406 ; free virtual = 17834 INFO: [BD::TCL 103-2004] Making design as current_bd_design. # common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." INFO: [BD::TCL 103-2005] Currently the variable is equal to "base". # if { $nRet != 0 } { # catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} # return $nRet # } # set bCheckIPsPassed 1 # set bCheckIPs 1 # if { $bCheckIPs == 1 } { # set list_check_ips "\ # xilinx.com:ip:axi_intc:4.1\ # xilinx.com:ip:axi_register_slice:2.1\ # xilinx.com:ip:axi_iic:2.0\ # xilinx.com:ip:axi_gpio:2.0\ # xilinx.com:ip:xlslice:1.0\ # xilinx.com:ip:mdm:3.2\ # xilinx.com:ip:util_ds_buf:2.1\ # xilinx.com:ip:proc_sys_reset:5.0\ # xilinx.com:ip:zynq_ultra_ps_e:3.3\ # xilinx.com:ip:dfx_axi_shutdown_manager:1.0\ # xilinx.com:ip:xlconstant:1.1\ # xilinx.com:ip:xlconcat:2.1\ # xilinx.com:user:dff_en_reset_vector:1.0\ # xilinx.com:user:io_switch:1.1\ # xilinx.com:ip:microblaze:11.0\ # xilinx.com:ip:axi_bram_ctrl:4.1\ # xilinx.com:ip:axi_quad_spi:3.2\ # xilinx.com:ip:axi_timer:2.0\ # xilinx.com:ip:axi_vdma:6.3\ # xilinx.com:ip:lmb_v10:3.0\ # xilinx.com:ip:blk_mem_gen:8.4\ # xilinx.com:ip:lmb_bram_if_cntlr:4.0\ # xilinx.com:hls:color_convert_2:1.0\ # xilinx.com:ip:v_hdmi_rx_ss:3.1\ # xilinx.com:hls:pixel_pack_2:1.0\ # xilinx.com:ip:axis_subset_converter:1.1\ # xilinx.com:ip:axis_register_slice:1.1\ # xilinx.com:ip:v_hdmi_tx_ss:3.1\ # xilinx.com:hls:pixel_unpack_2:1.0\ # xilinx.com:ip:vid_phy_controller:2.2\ # " # # set list_ips_missing "" # common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." # # foreach ip_vlnv $list_check_ips { # set ip_obj [get_ipdefs -all $ip_vlnv] # if { $ip_obj eq "" } { # lappend list_ips_missing $ip_vlnv # } # } # # if { $list_ips_missing ne "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } # set bCheckIPsPassed 0 # } # # } INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog: xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_register_slice:2.1 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:ip:dfx_axi_shutdown_manager:1.0 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:xlconcat:2.1 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:hls:color_convert_2:1.0 xilinx.com:ip:v_hdmi_rx_ss:3.1 xilinx.com:hls:pixel_pack_2:1.0 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:axis_register_slice:1.1 xilinx.com:ip:v_hdmi_tx_ss:3.1 xilinx.com:hls:pixel_unpack_2:1.0 xilinx.com:ip:vid_phy_controller:2.2 . # if { $bCheckIPsPassed != 1 } { # common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." # return 3 # } # proc create_hier_cell_phy { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_phy() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 DRU_CLK_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 vid_phy_axi4lite # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_rx_axi4s_ch0 # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_rx_axi4s_ch1 # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_rx_axi4s_ch2 # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_status_sb_rx # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_status_sb_tx # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_tx_axi4s_ch0 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_tx_axi4s_ch1 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 vid_phy_tx_axi4s_ch2 # # # # Create pins # create_bd_pin -dir I -type clk HDMI_RX_CLK_N_IN # create_bd_pin -dir I -type clk HDMI_RX_CLK_P_IN # create_bd_pin -dir I -from 2 -to 0 HDMI_RX_DAT_N_IN # create_bd_pin -dir I -from 2 -to 0 HDMI_RX_DAT_P_IN # create_bd_pin -dir O -type clk HDMI_TX_CLK_N_OUT # create_bd_pin -dir O -type clk HDMI_TX_CLK_P_OUT # create_bd_pin -dir O -from 2 -to 0 HDMI_TX_DAT_N_OUT # create_bd_pin -dir O -from 2 -to 0 HDMI_TX_DAT_P_OUT # create_bd_pin -dir I IDT_8T49N241_LOL_IN # create_bd_pin -dir O -type clk RX_REFCLK_N_OUT # create_bd_pin -dir O -type clk RX_REFCLK_P_OUT # create_bd_pin -dir I -type rst TX_EN_OUT # create_bd_pin -dir I -type clk TX_REFCLK_N_IN # create_bd_pin -dir I -type clk TX_REFCLK_P_IN # create_bd_pin -dir O -type intr irq2 # create_bd_pin -dir O -type clk rx_video_clk # create_bd_pin -dir I -type clk s_axi_cpu_aclk # create_bd_pin -dir I -type rst s_axi_cpu_aresetn # create_bd_pin -dir O -type clk tx_video_clk # create_bd_pin -dir O -type clk vid_phy_rx_axi4s_aclk # create_bd_pin -dir O -type clk vid_phy_tx_axi4s_aclk # # # Create instance: dru_ibufds_gt_odiv2, and set properties # set dru_ibufds_gt_odiv2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 dru_ibufds_gt_odiv2 ] # set_property -dict [ list \ # CONFIG.C_BUF_TYPE {BUFG_GT} \ # ] $dru_ibufds_gt_odiv2 # # # Create instance: gt_refclk_buf, and set properties # set gt_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 gt_refclk_buf ] # set_property -dict [ list \ # CONFIG.C_BUF_TYPE {IBUFDSGTE} \ # ] $gt_refclk_buf # # # Create instance: vcc_const0, and set properties # set vcc_const0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc_const0 ] # set_property -dict [ list \ # CONFIG.CONST_VAL {1} \ # ] $vcc_const0 # # # Create instance: vid_phy_controller, and set properties # set vid_phy_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:vid_phy_controller:2.2 vid_phy_controller ] # set_property -dict [ list \ # CONFIG.CHANNEL_ENABLE {X0Y16 X0Y17 X0Y18} \ # CONFIG.CHANNEL_SITE {X0Y16} \ # CONFIG.C_INPUT_PIXELS_PER_CLOCK {2} \ # CONFIG.C_INT_HDMI_VER_CMPTBLE {3} \ # CONFIG.C_NIDRU {true} \ # CONFIG.C_NIDRU_REFCLK_SEL {3} \ # CONFIG.C_RX_PLL_SELECTION {0} \ # CONFIG.C_RX_REFCLK_SEL {1} \ # CONFIG.C_Rx_Protocol {HDMI} \ # CONFIG.C_TX_PLL_SELECTION {6} \ # CONFIG.C_TX_REFCLK_SEL {0} \ # CONFIG.C_Tx_Protocol {HDMI} \ # CONFIG.C_Txrefclk_Rdy_Invert {true} \ # CONFIG.C_Use_Oddr_for_Tmds_Clkout {true} \ # CONFIG.C_vid_phy_rx_axi4s_ch_INT_TDATA_WIDTH {20} \ # CONFIG.C_vid_phy_rx_axi4s_ch_TDATA_WIDTH {20} \ # CONFIG.C_vid_phy_rx_axi4s_ch_TUSER_WIDTH {1} \ # CONFIG.C_vid_phy_tx_axi4s_ch_INT_TDATA_WIDTH {20} \ # CONFIG.C_vid_phy_tx_axi4s_ch_TDATA_WIDTH {20} \ # CONFIG.C_vid_phy_tx_axi4s_ch_TUSER_WIDTH {1} \ # CONFIG.Rx_GT_Line_Rate {5.94} \ # CONFIG.Rx_GT_Ref_Clock_Freq {297} \ # CONFIG.Transceiver_Width {2} \ # CONFIG.Tx_GT_Line_Rate {5.94} \ # CONFIG.Tx_GT_Ref_Clock_Freq {297} \ # ] $vid_phy_controller # # # Create interface connections # connect_bd_intf_net -intf_net intf_net_bdry_in_DRU_CLK_IN [get_bd_intf_pins DRU_CLK_IN] [get_bd_intf_pins gt_refclk_buf/CLK_IN_D] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA0_OUT [get_bd_intf_pins vid_phy_tx_axi4s_ch0] [get_bd_intf_pins vid_phy_controller/vid_phy_tx_axi4s_ch0] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA1_OUT [get_bd_intf_pins vid_phy_tx_axi4s_ch1] [get_bd_intf_pins vid_phy_controller/vid_phy_tx_axi4s_ch1] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA2_OUT [get_bd_intf_pins vid_phy_tx_axi4s_ch2] [get_bd_intf_pins vid_phy_controller/vid_phy_tx_axi4s_ch2] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch0 [get_bd_intf_pins vid_phy_rx_axi4s_ch0] [get_bd_intf_pins vid_phy_controller/vid_phy_rx_axi4s_ch0] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch1 [get_bd_intf_pins vid_phy_rx_axi4s_ch1] [get_bd_intf_pins vid_phy_controller/vid_phy_rx_axi4s_ch1] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch2 [get_bd_intf_pins vid_phy_rx_axi4s_ch2] [get_bd_intf_pins vid_phy_controller/vid_phy_rx_axi4s_ch2] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_rx [get_bd_intf_pins vid_phy_status_sb_rx] [get_bd_intf_pins vid_phy_controller/vid_phy_status_sb_rx] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_tx [get_bd_intf_pins vid_phy_status_sb_tx] [get_bd_intf_pins vid_phy_controller/vid_phy_status_sb_tx] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M00_AXI [get_bd_intf_pins vid_phy_axi4lite] [get_bd_intf_pins vid_phy_controller/vid_phy_axi4lite] # # # Create port connections # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_N_IN [get_bd_pins HDMI_RX_CLK_N_IN] [get_bd_pins vid_phy_controller/mgtrefclk1_pad_n_in] # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_P_IN [get_bd_pins HDMI_RX_CLK_P_IN] [get_bd_pins vid_phy_controller/mgtrefclk1_pad_p_in] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_N_IN [get_bd_pins HDMI_RX_DAT_N_IN] [get_bd_pins vid_phy_controller/phy_rxn_in] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_P_IN [get_bd_pins HDMI_RX_DAT_P_IN] [get_bd_pins vid_phy_controller/phy_rxp_in] # connect_bd_net -net net_bdry_in_IDT_8T49N241_LOL_IN [get_bd_pins IDT_8T49N241_LOL_IN] [get_bd_pins vid_phy_controller/tx_refclk_rdy] # connect_bd_net -net net_bdry_in_TX_REFCLK_N_IN [get_bd_pins TX_REFCLK_N_IN] [get_bd_pins vid_phy_controller/mgtrefclk0_pad_n_in] # connect_bd_net -net net_bdry_in_TX_REFCLK_P_IN [get_bd_pins TX_REFCLK_P_IN] [get_bd_pins vid_phy_controller/mgtrefclk0_pad_p_in] # connect_bd_net -net net_dru_ibufds_gt_odiv2_BUFG_GT_O [get_bd_pins dru_ibufds_gt_odiv2/BUFG_GT_O] [get_bd_pins vid_phy_controller/gtnorthrefclk1_odiv2_in] # connect_bd_net -net net_gt_refclk_buf_IBUF_DS_ODIV2 [get_bd_pins dru_ibufds_gt_odiv2/BUFG_GT_I] [get_bd_pins gt_refclk_buf/IBUF_DS_ODIV2] # connect_bd_net -net net_gt_refclk_buf_IBUF_OUT [get_bd_pins gt_refclk_buf/IBUF_OUT] [get_bd_pins vid_phy_controller/gtnorthrefclk1_in] # connect_bd_net -net net_vcc_const0_dout [get_bd_pins dru_ibufds_gt_odiv2/BUFG_GT_CE] [get_bd_pins vcc_const0/dout] # connect_bd_net -net net_vcc_const_dout [get_bd_pins TX_EN_OUT] [get_bd_pins vid_phy_controller/vid_phy_rx_axi4s_aresetn] [get_bd_pins vid_phy_controller/vid_phy_tx_axi4s_aresetn] # connect_bd_net -net net_vid_phy_controller_irq [get_bd_pins irq2] [get_bd_pins vid_phy_controller/irq] # connect_bd_net -net net_vid_phy_controller_phy_txn_out [get_bd_pins HDMI_TX_DAT_N_OUT] [get_bd_pins vid_phy_controller/phy_txn_out] # connect_bd_net -net net_vid_phy_controller_phy_txp_out [get_bd_pins HDMI_TX_DAT_P_OUT] [get_bd_pins vid_phy_controller/phy_txp_out] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_n [get_bd_pins RX_REFCLK_N_OUT] [get_bd_pins vid_phy_controller/rx_tmds_clk_n] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_p [get_bd_pins RX_REFCLK_P_OUT] [get_bd_pins vid_phy_controller/rx_tmds_clk_p] # connect_bd_net -net net_vid_phy_controller_rx_video_clk [get_bd_pins rx_video_clk] [get_bd_pins vid_phy_controller/rx_video_clk] # connect_bd_net -net net_vid_phy_controller_rxoutclk [get_bd_pins vid_phy_rx_axi4s_aclk] [get_bd_pins vid_phy_controller/rxoutclk] [get_bd_pins vid_phy_controller/vid_phy_rx_axi4s_aclk] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_n [get_bd_pins HDMI_TX_CLK_N_OUT] [get_bd_pins vid_phy_controller/tx_tmds_clk_n] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_p [get_bd_pins HDMI_TX_CLK_P_OUT] [get_bd_pins vid_phy_controller/tx_tmds_clk_p] # connect_bd_net -net net_vid_phy_controller_tx_video_clk [get_bd_pins tx_video_clk] [get_bd_pins vid_phy_controller/tx_video_clk] # connect_bd_net -net net_vid_phy_controller_txoutclk [get_bd_pins vid_phy_tx_axi4s_aclk] [get_bd_pins vid_phy_controller/txoutclk] [get_bd_pins vid_phy_controller/vid_phy_tx_axi4s_aclk] # connect_bd_net -net net_zynq_us_ss_0_peripheral_aresetn [get_bd_pins s_axi_cpu_aresetn] [get_bd_pins vid_phy_controller/vid_phy_axi4lite_aresetn] [get_bd_pins vid_phy_controller/vid_phy_sb_aresetn] # connect_bd_net -net net_zynq_us_ss_0_s_axi_aclk [get_bd_pins s_axi_cpu_aclk] [get_bd_pins vid_phy_controller/drpclk] [get_bd_pins vid_phy_controller/vid_phy_axi4lite_aclk] [get_bd_pins vid_phy_controller/vid_phy_sb_aclk] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_hdmi_out { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hdmi_out() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA0_OUT # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA1_OUT # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA2_OUT # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 SB_STATUS_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CPU_IN # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 TX_DDC_OUT # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS1 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 stream_in_64 # # # # Create pins # create_bd_pin -dir I TX_HPD_IN # create_bd_pin -dir I -type clk aclk # create_bd_pin -dir I acr_valid # create_bd_pin -dir I -type rst aresetn # create_bd_pin -dir I fid # create_bd_pin -dir O -type intr irq1 # create_bd_pin -dir I -type clk link_clk # create_bd_pin -dir I -type clk s_axi_cpu_aclk # create_bd_pin -dir I -type rst s_axi_cpu_aresetn # create_bd_pin -dir I -type clk s_axis_audio_aclk # create_bd_pin -dir I -type rst s_axis_audio_aresetn # create_bd_pin -dir I -type clk video_clk # # # Create instance: color_convert, and set properties # set color_convert [ create_bd_cell -type ip -vlnv xilinx.com:hls:color_convert_2:1.0 color_convert ] # # # Create instance: frontend, and set properties # set frontend [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_hdmi_tx_ss:3.1 frontend ] # set_property -dict [ list \ # CONFIG.C_ADDR_WIDTH {13} \ # CONFIG.C_ADD_MARK_DBG {false} \ # CONFIG.C_EXDES_AXILITE_FREQ {100} \ # CONFIG.C_EXDES_NIDRU {true} \ # CONFIG.C_EXDES_RX_PLL_SELECTION {0} \ # CONFIG.C_EXDES_TOPOLOGY {0} \ # CONFIG.C_EXDES_TX_PLL_SELECTION {6} \ # CONFIG.C_HDMI_FAST_SWITCH {true} \ # CONFIG.C_HDMI_VERSION {3} \ # CONFIG.C_HPD_INVERT {false} \ # CONFIG.C_HYSTERESIS_LEVEL {12} \ # CONFIG.C_INCLUDE_HDCP_1_4 {false} \ # CONFIG.C_INCLUDE_HDCP_2_2 {false} \ # CONFIG.C_INCLUDE_LOW_RESO_VID {false} \ # CONFIG.C_INCLUDE_YUV420_SUP {false} \ # CONFIG.C_INPUT_PIXELS_PER_CLOCK {2} \ # CONFIG.C_MAX_BITS_PER_COMPONENT {8} \ # CONFIG.C_VALIDATION_ENABLE {false} \ # CONFIG.C_VIDEO_MASK_ENABLE {1} \ # CONFIG.C_VID_INTERFACE {0} \ # ] $frontend # # # Create instance: pixel_reorder, and set properties # set pixel_reorder [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 pixel_reorder ] # set_property -dict [ list \ # CONFIG.M_TDATA_NUM_BYTES {6} \ # CONFIG.S_TDATA_NUM_BYTES {6} \ # CONFIG.TDATA_REMAP {tdata[47:40],tdata[31:24],tdata[39:32],tdata[23:16],tdata[7:0],tdata[15:8]} \ # CONFIG.TLAST_REMAP {1'b0} \ # CONFIG.TUSER_REMAP {1'b0} \ # ] $pixel_reorder # # # Create instance: pixel_unpack, and set properties # set pixel_unpack [ create_bd_cell -type ip -vlnv xilinx.com:hls:pixel_unpack_2:1.0 pixel_unpack ] # # # Create instance: tx_video_axis_reg_slice, and set properties # set tx_video_axis_reg_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 tx_video_axis_reg_slice ] # # # Create interface connections # connect_bd_intf_net -intf_net axi_interconnect_M07_AXI [get_bd_intf_pins s_axi_AXILiteS] [get_bd_intf_pins color_convert/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_interconnect_M10_AXI [get_bd_intf_pins s_axi_AXILiteS1] [get_bd_intf_pins pixel_unpack/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins stream_in_64] [get_bd_intf_pins pixel_unpack/stream_in_64] # connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins frontend/VIDEO_IN] [get_bd_intf_pins pixel_reorder/M_AXIS] # connect_bd_intf_net -intf_net color_convert_0_stream_out_48 [get_bd_intf_pins color_convert/stream_out_48] [get_bd_intf_pins tx_video_axis_reg_slice/S_AXIS] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_DDC_OUT [get_bd_intf_pins TX_DDC_OUT] [get_bd_intf_pins frontend/DDC_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA0_OUT [get_bd_intf_pins LINK_DATA0_OUT] [get_bd_intf_pins frontend/LINK_DATA0_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA1_OUT [get_bd_intf_pins LINK_DATA1_OUT] [get_bd_intf_pins frontend/LINK_DATA1_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA2_OUT [get_bd_intf_pins LINK_DATA2_OUT] [get_bd_intf_pins frontend/LINK_DATA2_OUT] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_tx [get_bd_intf_pins SB_STATUS_IN] [get_bd_intf_pins frontend/SB_STATUS_IN] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M02_AXI [get_bd_intf_pins S_AXI_CPU_IN] [get_bd_intf_pins frontend/S_AXI_CPU_IN] # connect_bd_intf_net -intf_net pixel_unpack_0_stream_out_48 [get_bd_intf_pins color_convert/stream_in_48] [get_bd_intf_pins pixel_unpack/stream_out_48] # connect_bd_intf_net -intf_net tx_video_axis_reg_slice_M_AXIS [get_bd_intf_pins pixel_reorder/S_AXIS] [get_bd_intf_pins tx_video_axis_reg_slice/M_AXIS] # # # Create port connections # connect_bd_net -net acr_valid_1 [get_bd_pins acr_valid] [get_bd_pins frontend/acr_valid] # connect_bd_net -net net_bdry_in_TX_HPD_IN [get_bd_pins TX_HPD_IN] [get_bd_pins frontend/hpd] # connect_bd_net -net net_v_hdmi_rx_ss_fid [get_bd_pins fid] [get_bd_pins frontend/fid] # connect_bd_net -net net_v_hdmi_tx_ss_irq [get_bd_pins irq1] [get_bd_pins frontend/irq] # connect_bd_net -net net_v_hdmi_tx_ss_locked [get_bd_pins frontend/locked] # connect_bd_net -net net_vid_phy_controller_tx_video_clk [get_bd_pins video_clk] [get_bd_pins frontend/video_clk] # connect_bd_net -net net_vid_phy_controller_txoutclk [get_bd_pins link_clk] [get_bd_pins frontend/link_clk] # connect_bd_net -net net_zynq_us_ss_0_clk_out2 [get_bd_pins aclk] [get_bd_pins color_convert/ap_clk] [get_bd_pins color_convert/control] [get_bd_pins frontend/s_axis_video_aclk] [get_bd_pins pixel_reorder/aclk] [get_bd_pins pixel_unpack/ap_clk] [get_bd_pins pixel_unpack/control] [get_bd_pins tx_video_axis_reg_slice/aclk] # connect_bd_net -net net_zynq_us_ss_0_dcm_locked [get_bd_pins aresetn] [get_bd_pins color_convert/ap_rst_n] [get_bd_pins color_convert/ap_rst_n_control] [get_bd_pins frontend/s_axis_video_aresetn] [get_bd_pins pixel_reorder/aresetn] [get_bd_pins pixel_unpack/ap_rst_n] [get_bd_pins pixel_unpack/ap_rst_n_control] [get_bd_pins tx_video_axis_reg_slice/aresetn] # connect_bd_net -net net_zynq_us_ss_0_peripheral_aresetn [get_bd_pins s_axi_cpu_aresetn] [get_bd_pins frontend/s_axi_cpu_aresetn] # connect_bd_net -net net_zynq_us_ss_0_s_axi_aclk [get_bd_pins s_axi_cpu_aclk] [get_bd_pins frontend/s_axi_cpu_aclk] # connect_bd_net -net s_axis_audio_aclk_1 [get_bd_pins s_axis_audio_aclk] [get_bd_pins frontend/s_axis_audio_aclk] # connect_bd_net -net s_axis_audio_aresetn_1 [get_bd_pins s_axis_audio_aresetn] [get_bd_pins frontend/s_axis_audio_aresetn] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_hdmi_in { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hdmi_in() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA0_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA1_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 LINK_DATA2_IN # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 RX_DDC_OUT # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 SB_STATUS_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CPU_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS1 # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 stream_out_64 # # # # Create pins # create_bd_pin -dir I RX_DET_IN # create_bd_pin -dir O RX_HPD_OUT # create_bd_pin -dir I -type clk aclk # create_bd_pin -dir I -type rst aresetn # create_bd_pin -dir O fid # create_bd_pin -dir O -type intr irq # create_bd_pin -dir I -type clk link_clk # create_bd_pin -dir I -type clk s_axi_cpu_aclk # create_bd_pin -dir I -type rst s_axi_cpu_aresetn # create_bd_pin -dir I -type clk s_axis_audio_aclk # create_bd_pin -dir I -type rst s_axis_audio_aresetn # create_bd_pin -dir I -type clk video_clk # # # Create instance: color_convert, and set properties # set color_convert [ create_bd_cell -type ip -vlnv xilinx.com:hls:color_convert_2:1.0 color_convert ] # # # Create instance: frontend, and set properties # set frontend [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_hdmi_rx_ss:3.1 frontend ] # set_property -dict [ list \ # CONFIG.C_ADDR_WIDTH {10} \ # CONFIG.C_ADD_MARK_DBG {false} \ # CONFIG.C_CD_INVERT {true} \ # CONFIG.C_EDID_RAM_SIZE {256} \ # CONFIG.C_HDMI_FAST_SWITCH {true} \ # CONFIG.C_HDMI_VERSION {3} \ # CONFIG.C_HPD_INVERT {false} \ # CONFIG.C_INCLUDE_HDCP_1_4 {false} \ # CONFIG.C_INCLUDE_HDCP_2_2 {false} \ # CONFIG.C_INCLUDE_LOW_RESO_VID {false} \ # CONFIG.C_INCLUDE_YUV420_SUP {false} \ # CONFIG.C_INPUT_PIXELS_PER_CLOCK {2} \ # CONFIG.C_MAX_BITS_PER_COMPONENT {8} \ # CONFIG.C_VALIDATION_ENABLE {false} \ # CONFIG.C_VID_INTERFACE {0} \ # ] $frontend # # # Create instance: pixel_pack, and set properties # set pixel_pack [ create_bd_cell -type ip -vlnv xilinx.com:hls:pixel_pack_2:1.0 pixel_pack ] # # # Create instance: pixel_reorder, and set properties # set pixel_reorder [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 pixel_reorder ] # set_property -dict [ list \ # CONFIG.M_TDATA_NUM_BYTES {6} \ # CONFIG.S_TDATA_NUM_BYTES {6} \ # CONFIG.TDATA_REMAP {tdata[47:40],tdata[31:24],tdata[39:32],tdata[23:16],tdata[7:0],tdata[15:8]} \ # CONFIG.TLAST_REMAP {1'b0} \ # CONFIG.TUSER_REMAP {1'b0} \ # ] $pixel_reorder # # # Create instance: rx_video_axis_reg_slice, and set properties # set rx_video_axis_reg_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 rx_video_axis_reg_slice ] # # # Create interface connections # connect_bd_intf_net -intf_net axi_interconnect_M08_AXI [get_bd_intf_pins s_axi_AXILiteS] [get_bd_intf_pins color_convert/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_interconnect_M09_AXI [get_bd_intf_pins s_axi_AXILiteS1] [get_bd_intf_pins pixel_pack/s_axi_AXILiteS] # connect_bd_intf_net -intf_net color_convert_1_stream_out_48 [get_bd_intf_pins color_convert/stream_out_48] [get_bd_intf_pins pixel_pack/stream_in_48] # connect_bd_intf_net -intf_net frontend_VIDEO_OUT [get_bd_intf_pins frontend/VIDEO_OUT] [get_bd_intf_pins pixel_reorder/S_AXIS] # connect_bd_intf_net -intf_net intf_net_v_hdmi_rx_ss_DDC_OUT [get_bd_intf_pins RX_DDC_OUT] [get_bd_intf_pins frontend/DDC_OUT] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch0 [get_bd_intf_pins LINK_DATA0_IN] [get_bd_intf_pins frontend/LINK_DATA0_IN] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch1 [get_bd_intf_pins LINK_DATA1_IN] [get_bd_intf_pins frontend/LINK_DATA1_IN] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch2 [get_bd_intf_pins LINK_DATA2_IN] [get_bd_intf_pins frontend/LINK_DATA2_IN] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_rx [get_bd_intf_pins SB_STATUS_IN] [get_bd_intf_pins frontend/SB_STATUS_IN] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M01_AXI [get_bd_intf_pins S_AXI_CPU_IN] [get_bd_intf_pins frontend/S_AXI_CPU_IN] # connect_bd_intf_net -intf_net pixel_pack_0_stream_out_64 [get_bd_intf_pins stream_out_64] [get_bd_intf_pins pixel_pack/stream_out_64] # connect_bd_intf_net -intf_net pixel_reorder_M_AXIS [get_bd_intf_pins pixel_reorder/M_AXIS] [get_bd_intf_pins rx_video_axis_reg_slice/S_AXIS] # connect_bd_intf_net -intf_net rx_video_axis_reg_slice_M_AXIS [get_bd_intf_pins color_convert/stream_in_48] [get_bd_intf_pins rx_video_axis_reg_slice/M_AXIS] # # # Create port connections # connect_bd_net -net net_bdry_in_RX_DET_IN [get_bd_pins RX_DET_IN] [get_bd_pins frontend/cable_detect] # connect_bd_net -net net_v_hdmi_rx_ss_fid [get_bd_pins fid] [get_bd_pins frontend/fid] # connect_bd_net -net net_v_hdmi_rx_ss_hpd [get_bd_pins RX_HPD_OUT] [get_bd_pins frontend/hpd] # connect_bd_net -net net_v_hdmi_rx_ss_irq [get_bd_pins irq] [get_bd_pins frontend/irq] # connect_bd_net -net net_vid_phy_controller_rx_video_clk [get_bd_pins video_clk] [get_bd_pins frontend/video_clk] # connect_bd_net -net net_vid_phy_controller_rxoutclk [get_bd_pins link_clk] [get_bd_pins frontend/link_clk] # connect_bd_net -net net_zynq_us_ss_0_clk_out2 [get_bd_pins aclk] [get_bd_pins color_convert/ap_clk] [get_bd_pins color_convert/control] [get_bd_pins frontend/s_axis_video_aclk] [get_bd_pins pixel_pack/ap_clk] [get_bd_pins pixel_pack/control] [get_bd_pins pixel_reorder/aclk] [get_bd_pins rx_video_axis_reg_slice/aclk] # connect_bd_net -net net_zynq_us_ss_0_dcm_locked [get_bd_pins aresetn] [get_bd_pins color_convert/ap_rst_n] [get_bd_pins color_convert/ap_rst_n_control] [get_bd_pins frontend/s_axis_video_aresetn] [get_bd_pins pixel_pack/ap_rst_n] [get_bd_pins pixel_pack/ap_rst_n_control] [get_bd_pins pixel_reorder/aresetn] [get_bd_pins rx_video_axis_reg_slice/aresetn] # connect_bd_net -net net_zynq_us_ss_0_peripheral_aresetn [get_bd_pins s_axi_cpu_aresetn] [get_bd_pins frontend/s_axi_cpu_aresetn] # connect_bd_net -net net_zynq_us_ss_0_s_axi_aclk [get_bd_pins s_axi_cpu_aclk] [get_bd_pins frontend/s_axi_cpu_aclk] # connect_bd_net -net s_axis_audio_aclk_1 [get_bd_pins s_axis_audio_aclk] [get_bd_pins frontend/s_axis_audio_aclk] # connect_bd_net -net s_axis_audio_aresetn_1 [get_bd_pins s_axis_audio_aresetn] [get_bd_pins frontend/s_axis_audio_aresetn] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_lmb_1 { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_lmb_1() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTB # # create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB # # create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB # # # # Create pins # create_bd_pin -dir I -type clk LMB_Clk # create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst # # # Create instance: dlmb_v10, and set properties # set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] # # # Create instance: ilmb_v10, and set properties # set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] # # # Create instance: lmb_bram, and set properties # set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] # set_property -dict [ list \ # CONFIG.Enable_B {Use_ENB_Pin} \ # CONFIG.Memory_Type {True_Dual_Port_RAM} \ # CONFIG.Port_B_Clock {100} \ # CONFIG.Port_B_Enable_Rate {100} \ # CONFIG.Port_B_Write_Rate {50} \ # CONFIG.Use_RSTB_Pin {true} \ # CONFIG.use_bram_block {BRAM_Controller} \ # ] $lmb_bram # # # Create instance: lmb_bram_if_cntlr, and set properties # set lmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 lmb_bram_if_cntlr ] # set_property -dict [ list \ # CONFIG.C_ECC {0} \ # CONFIG.C_NUM_LMB {2} \ # ] $lmb_bram_if_cntlr # # # Create interface connections # connect_bd_intf_net -intf_net Conn [get_bd_intf_pins dlmb_v10/LMB_Sl_0] [get_bd_intf_pins lmb_bram_if_cntlr/SLMB1] # connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins BRAM_PORTB] [get_bd_intf_pins lmb_bram/BRAM_PORTB] # connect_bd_intf_net -intf_net lmb_bram_if_cntlr_BRAM_PORT [get_bd_intf_pins lmb_bram/BRAM_PORTA] [get_bd_intf_pins lmb_bram_if_cntlr/BRAM_PORT] # connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] # connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] # connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_v10/LMB_Sl_0] [get_bd_intf_pins lmb_bram_if_cntlr/SLMB] # # # Create port connections # connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_v10/SYS_Rst] [get_bd_pins lmb_bram_if_cntlr/LMB_Rst] # connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] [get_bd_pins lmb_bram_if_cntlr/LMB_Clk] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_lmb { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_lmb() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:bram_rtl:1.0 BRAM_PORTB # # create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB # # create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB # # # # Create pins # create_bd_pin -dir I -type clk LMB_Clk # create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst # # # Create instance: dlmb_v10, and set properties # set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] # # # Create instance: ilmb_v10, and set properties # set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] # # # Create instance: lmb_bram, and set properties # set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] # set_property -dict [ list \ # CONFIG.Enable_B {Use_ENB_Pin} \ # CONFIG.Memory_Type {True_Dual_Port_RAM} \ # CONFIG.Port_B_Clock {100} \ # CONFIG.Port_B_Enable_Rate {100} \ # CONFIG.Port_B_Write_Rate {50} \ # CONFIG.Use_RSTB_Pin {true} \ # CONFIG.use_bram_block {BRAM_Controller} \ # ] $lmb_bram # # # Create instance: lmb_bram_if_cntlr, and set properties # set lmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 lmb_bram_if_cntlr ] # set_property -dict [ list \ # CONFIG.C_ECC {0} \ # CONFIG.C_NUM_LMB {2} \ # ] $lmb_bram_if_cntlr # # # Create interface connections # connect_bd_intf_net -intf_net Conn [get_bd_intf_pins dlmb_v10/LMB_Sl_0] [get_bd_intf_pins lmb_bram_if_cntlr/SLMB1] # connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins BRAM_PORTB] [get_bd_intf_pins lmb_bram/BRAM_PORTB] # connect_bd_intf_net -intf_net lmb_bram_if_cntlr_BRAM_PORT [get_bd_intf_pins lmb_bram/BRAM_PORTA] [get_bd_intf_pins lmb_bram_if_cntlr/BRAM_PORT] # connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] # connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] # connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_v10/LMB_Sl_0] [get_bd_intf_pins lmb_bram_if_cntlr/SLMB] # # # Create port connections # connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_v10/SYS_Rst] [get_bd_pins lmb_bram_if_cntlr/LMB_Rst] # connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] [get_bd_pins lmb_bram_if_cntlr/LMB_Clk] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_video { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_video() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 DRU_CLK_IN # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 RX_DDC_OUT # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CPU_IN # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_CPU_IN1 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_LITE # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 TX_DDC_OUT # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS1 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS2 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_AXILiteS3 # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 vid_phy_axi4lite # # # # Create pins # create_bd_pin -dir I -type clk HDMI_RX_CLK_N_IN # create_bd_pin -dir I -type clk HDMI_RX_CLK_P_IN # create_bd_pin -dir I -from 2 -to 0 HDMI_RX_DAT_N_IN # create_bd_pin -dir I -from 2 -to 0 HDMI_RX_DAT_P_IN # create_bd_pin -dir O -type clk HDMI_TX_CLK_N_OUT # create_bd_pin -dir O -type clk HDMI_TX_CLK_P_OUT # create_bd_pin -dir O -from 2 -to 0 HDMI_TX_DAT_N_OUT # create_bd_pin -dir O -from 2 -to 0 HDMI_TX_DAT_P_OUT # create_bd_pin -dir I IDT_8T49N241_LOL_IN # create_bd_pin -dir I RX_DET_IN # create_bd_pin -dir O RX_HPD_OUT # create_bd_pin -dir O -type clk RX_REFCLK_N_OUT # create_bd_pin -dir O -type clk RX_REFCLK_P_OUT # create_bd_pin -dir I -type rst TX_EN_OUT # create_bd_pin -dir I TX_HPD_IN # create_bd_pin -dir I -type clk TX_REFCLK_N_IN # create_bd_pin -dir I -type clk TX_REFCLK_P_IN # create_bd_pin -dir I -type clk aclk # create_bd_pin -dir I -type rst aresetn # create_bd_pin -dir O -type intr irq # create_bd_pin -dir O -type intr irq1 # create_bd_pin -dir O -type intr irq2 # create_bd_pin -dir O -type intr mm2s_introut # create_bd_pin -dir O -type intr s2mm_introut # create_bd_pin -dir I -type clk s_axi_cpu_aclk # create_bd_pin -dir I -type rst s_axi_cpu_aresetn # # # Create instance: axi_vdma, and set properties # set axi_vdma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma ] # set_property -dict [ list \ # CONFIG.c_m_axi_mm2s_data_width {128} \ # CONFIG.c_m_axi_s2mm_data_width {128} \ # CONFIG.c_m_axis_mm2s_tdata_width {64} \ # CONFIG.c_mm2s_linebuffer_depth {4096} \ # CONFIG.c_mm2s_max_burst_length {256} \ # CONFIG.c_num_fstores {4} \ # CONFIG.c_s2mm_linebuffer_depth {4096} \ # CONFIG.c_s2mm_max_burst_length {256} \ # ] $axi_vdma # # # Create instance: const_gnd, and set properties # set const_gnd [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_gnd ] # set_property -dict [ list \ # CONFIG.CONST_VAL {0} \ # ] $const_gnd # # # Create instance: hdmi_in # create_hier_cell_hdmi_in $hier_obj hdmi_in # # # Create instance: hdmi_out # create_hier_cell_hdmi_out $hier_obj hdmi_out # # # Create instance: phy # create_hier_cell_phy $hier_obj phy # # # Create interface connections # connect_bd_intf_net -intf_net axi_interconnect_M07_AXI [get_bd_intf_pins s_axi_AXILiteS] [get_bd_intf_pins hdmi_out/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_interconnect_M08_AXI [get_bd_intf_pins s_axi_AXILiteS1] [get_bd_intf_pins hdmi_in/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_interconnect_M09_AXI [get_bd_intf_pins s_axi_AXILiteS2] [get_bd_intf_pins hdmi_in/s_axi_AXILiteS1] # connect_bd_intf_net -intf_net axi_interconnect_M10_AXI [get_bd_intf_pins s_axi_AXILiteS3] [get_bd_intf_pins hdmi_out/s_axi_AXILiteS1] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma/M_AXIS_MM2S] [get_bd_intf_pins hdmi_out/stream_in_64] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins axi_vdma/M_AXI_MM2S] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins axi_vdma/M_AXI_S2MM] # connect_bd_intf_net -intf_net intf_net_bdry_in_DRU_CLK_IN [get_bd_intf_pins DRU_CLK_IN] [get_bd_intf_pins phy/DRU_CLK_IN] # connect_bd_intf_net -intf_net intf_net_v_hdmi_rx_ss_DDC_OUT [get_bd_intf_pins RX_DDC_OUT] [get_bd_intf_pins hdmi_in/RX_DDC_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_DDC_OUT [get_bd_intf_pins TX_DDC_OUT] [get_bd_intf_pins hdmi_out/TX_DDC_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA0_OUT [get_bd_intf_pins hdmi_out/LINK_DATA0_OUT] [get_bd_intf_pins phy/vid_phy_tx_axi4s_ch0] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA1_OUT [get_bd_intf_pins hdmi_out/LINK_DATA1_OUT] [get_bd_intf_pins phy/vid_phy_tx_axi4s_ch1] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_LINK_DATA2_OUT [get_bd_intf_pins hdmi_out/LINK_DATA2_OUT] [get_bd_intf_pins phy/vid_phy_tx_axi4s_ch2] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch0 [get_bd_intf_pins hdmi_in/LINK_DATA0_IN] [get_bd_intf_pins phy/vid_phy_rx_axi4s_ch0] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch1 [get_bd_intf_pins hdmi_in/LINK_DATA1_IN] [get_bd_intf_pins phy/vid_phy_rx_axi4s_ch1] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_rx_axi4s_ch2 [get_bd_intf_pins hdmi_in/LINK_DATA2_IN] [get_bd_intf_pins phy/vid_phy_rx_axi4s_ch2] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_rx [get_bd_intf_pins hdmi_in/SB_STATUS_IN] [get_bd_intf_pins phy/vid_phy_status_sb_rx] # connect_bd_intf_net -intf_net intf_net_vid_phy_controller_vid_phy_status_sb_tx [get_bd_intf_pins hdmi_out/SB_STATUS_IN] [get_bd_intf_pins phy/vid_phy_status_sb_tx] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M00_AXI [get_bd_intf_pins vid_phy_axi4lite] [get_bd_intf_pins phy/vid_phy_axi4lite] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M01_AXI [get_bd_intf_pins S_AXI_CPU_IN] [get_bd_intf_pins hdmi_in/S_AXI_CPU_IN] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M02_AXI [get_bd_intf_pins S_AXI_CPU_IN1] [get_bd_intf_pins hdmi_out/S_AXI_CPU_IN] # connect_bd_intf_net -intf_net pixel_pack_0_stream_out_64 [get_bd_intf_pins axi_vdma/S_AXIS_S2MM] [get_bd_intf_pins hdmi_in/stream_out_64] # connect_bd_intf_net -intf_net zynq_us_ss_0_M03_AXI [get_bd_intf_pins S_AXI_LITE] [get_bd_intf_pins axi_vdma/S_AXI_LITE] # # # Create port connections # connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins mm2s_introut] [get_bd_pins axi_vdma/mm2s_introut] # connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins axi_vdma/s2mm_introut] # connect_bd_net -net const_gnd_dout [get_bd_pins const_gnd/dout] [get_bd_pins hdmi_in/s_axis_audio_aclk] [get_bd_pins hdmi_in/s_axis_audio_aresetn] [get_bd_pins hdmi_out/acr_valid] [get_bd_pins hdmi_out/s_axis_audio_aclk] [get_bd_pins hdmi_out/s_axis_audio_aresetn] # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_N_IN [get_bd_pins HDMI_RX_CLK_N_IN] [get_bd_pins phy/HDMI_RX_CLK_N_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_P_IN [get_bd_pins HDMI_RX_CLK_P_IN] [get_bd_pins phy/HDMI_RX_CLK_P_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_N_IN [get_bd_pins HDMI_RX_DAT_N_IN] [get_bd_pins phy/HDMI_RX_DAT_N_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_P_IN [get_bd_pins HDMI_RX_DAT_P_IN] [get_bd_pins phy/HDMI_RX_DAT_P_IN] # connect_bd_net -net net_bdry_in_IDT_8T49N241_LOL_IN [get_bd_pins IDT_8T49N241_LOL_IN] [get_bd_pins phy/IDT_8T49N241_LOL_IN] # connect_bd_net -net net_bdry_in_RX_DET_IN [get_bd_pins RX_DET_IN] [get_bd_pins hdmi_in/RX_DET_IN] # connect_bd_net -net net_bdry_in_TX_HPD_IN [get_bd_pins TX_HPD_IN] [get_bd_pins hdmi_out/TX_HPD_IN] # connect_bd_net -net net_bdry_in_TX_REFCLK_N_IN [get_bd_pins TX_REFCLK_N_IN] [get_bd_pins phy/TX_REFCLK_N_IN] # connect_bd_net -net net_bdry_in_TX_REFCLK_P_IN [get_bd_pins TX_REFCLK_P_IN] [get_bd_pins phy/TX_REFCLK_P_IN] # connect_bd_net -net net_v_hdmi_rx_ss_hpd [get_bd_pins RX_HPD_OUT] [get_bd_pins hdmi_in/RX_HPD_OUT] # connect_bd_net -net net_v_hdmi_rx_ss_irq [get_bd_pins irq] [get_bd_pins hdmi_in/irq] # connect_bd_net -net net_v_hdmi_tx_ss_irq [get_bd_pins irq1] [get_bd_pins hdmi_out/irq1] # connect_bd_net -net net_vcc_const_dout [get_bd_pins TX_EN_OUT] [get_bd_pins phy/TX_EN_OUT] # connect_bd_net -net net_vid_phy_controller_irq [get_bd_pins irq2] [get_bd_pins phy/irq2] # connect_bd_net -net net_vid_phy_controller_phy_txn_out [get_bd_pins HDMI_TX_DAT_N_OUT] [get_bd_pins phy/HDMI_TX_DAT_N_OUT] # connect_bd_net -net net_vid_phy_controller_phy_txp_out [get_bd_pins HDMI_TX_DAT_P_OUT] [get_bd_pins phy/HDMI_TX_DAT_P_OUT] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_n [get_bd_pins RX_REFCLK_N_OUT] [get_bd_pins phy/RX_REFCLK_N_OUT] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_p [get_bd_pins RX_REFCLK_P_OUT] [get_bd_pins phy/RX_REFCLK_P_OUT] # connect_bd_net -net net_vid_phy_controller_rx_video_clk [get_bd_pins hdmi_in/video_clk] [get_bd_pins phy/rx_video_clk] # connect_bd_net -net net_vid_phy_controller_rxoutclk [get_bd_pins hdmi_in/link_clk] [get_bd_pins phy/vid_phy_rx_axi4s_aclk] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_n [get_bd_pins HDMI_TX_CLK_N_OUT] [get_bd_pins phy/HDMI_TX_CLK_N_OUT] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_p [get_bd_pins HDMI_TX_CLK_P_OUT] [get_bd_pins phy/HDMI_TX_CLK_P_OUT] # connect_bd_net -net net_vid_phy_controller_tx_video_clk [get_bd_pins hdmi_out/video_clk] [get_bd_pins phy/tx_video_clk] # connect_bd_net -net net_vid_phy_controller_txoutclk [get_bd_pins hdmi_out/link_clk] [get_bd_pins phy/vid_phy_tx_axi4s_aclk] # connect_bd_net -net net_zynq_us_ss_0_clk_out2 [get_bd_pins aclk] [get_bd_pins axi_vdma/m_axi_mm2s_aclk] [get_bd_pins axi_vdma/m_axi_s2mm_aclk] [get_bd_pins axi_vdma/m_axis_mm2s_aclk] [get_bd_pins axi_vdma/s_axis_s2mm_aclk] [get_bd_pins hdmi_in/aclk] [get_bd_pins hdmi_out/aclk] # connect_bd_net -net net_zynq_us_ss_0_dcm_locked [get_bd_pins aresetn] [get_bd_pins hdmi_in/aresetn] [get_bd_pins hdmi_out/aresetn] # connect_bd_net -net net_zynq_us_ss_0_peripheral_aresetn [get_bd_pins s_axi_cpu_aresetn] [get_bd_pins axi_vdma/axi_resetn] [get_bd_pins hdmi_in/s_axi_cpu_aresetn] [get_bd_pins hdmi_out/s_axi_cpu_aresetn] [get_bd_pins phy/s_axi_cpu_aresetn] # connect_bd_net -net net_zynq_us_ss_0_s_axi_aclk [get_bd_pins s_axi_cpu_aclk] [get_bd_pins axi_vdma/s_axi_lite_aclk] [get_bd_pins hdmi_in/s_axi_cpu_aclk] [get_bd_pins hdmi_out/s_axi_cpu_aclk] [get_bd_pins phy/s_axi_cpu_aclk] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_iop_pmod1 { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_iop_pmod1() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:mbdebug_rtl:3.0 DEBUG # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI # # # # Create pins # create_bd_pin -dir I -from 0 -to 0 -type rst aux_reset_in # create_bd_pin -dir I -type clk clk_100M # create_bd_pin -dir I -from 7 -to 0 data_i # create_bd_pin -dir O -from 7 -to 0 data_o # create_bd_pin -dir I -from 0 -to 0 intr_ack # create_bd_pin -dir O -from 0 -to 0 intr_req # create_bd_pin -dir I -type rst mb_debug_sys_rst # create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn # create_bd_pin -dir I -from 0 -to 0 -type rst s_axi_aresetn # create_bd_pin -dir O -from 7 -to 0 tri_o # # # Create instance: dff_en_reset_vector_0, and set properties # set dff_en_reset_vector_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dff_en_reset_vector:1.0 dff_en_reset_vector_0 ] # set_property -dict [ list \ # CONFIG.SIZE {1} \ # ] $dff_en_reset_vector_0 # # # Create instance: gpio, and set properties # set gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio ] # set_property -dict [ list \ # CONFIG.C_ALL_OUTPUTS_2 {0} \ # CONFIG.C_GPIO2_WIDTH {32} \ # CONFIG.C_GPIO_WIDTH {8} \ # CONFIG.C_IS_DUAL {0} \ # ] $gpio # # # Create instance: iic, and set properties # set iic [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic ] # # # Create instance: intc, and set properties # set intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 intc ] # # # Create instance: intr, and set properties # set intr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 intr ] # set_property -dict [ list \ # CONFIG.C_ALL_OUTPUTS {1} \ # CONFIG.C_GPIO_WIDTH {1} \ # ] $intr # # # Create instance: intr_concat, and set properties # set intr_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat ] # set_property -dict [ list \ # CONFIG.NUM_PORTS {3} \ # ] $intr_concat # # # Create instance: io_switch, and set properties # set io_switch [ create_bd_cell -type ip -vlnv xilinx.com:user:io_switch:1.1 io_switch ] # set_property -dict [ list \ # CONFIG.C_INTERFACE_TYPE {1} \ # CONFIG.C_IO_SWITCH_WIDTH {8} \ # CONFIG.C_NUM_PWMS {1} \ # CONFIG.C_NUM_TIMERS {1} \ # CONFIG.I2C0_Enable {true} \ # CONFIG.PWM_Enable {true} \ # CONFIG.SPI0_Enable {true} \ # CONFIG.Timer_Enable {true} \ # ] $io_switch # # # Create instance: lmb # create_hier_cell_lmb_1 $hier_obj lmb # # # Create instance: logic_1, and set properties # set logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 logic_1 ] # # # Create instance: mb, and set properties # set mb [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 mb ] # set_property -dict [ list \ # CONFIG.C_DEBUG_ENABLED {1} \ # CONFIG.C_D_AXI {1} \ # CONFIG.C_D_LMB {1} \ # CONFIG.C_I_LMB {1} \ # ] $mb # # # Create instance: mb_bram_ctrl, and set properties # set mb_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 mb_bram_ctrl ] # set_property -dict [ list \ # CONFIG.SINGLE_PORT_BRAM {1} \ # ] $mb_bram_ctrl # # # Create instance: microblaze_0_axi_periph, and set properties # set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] # set_property -dict [ list \ # CONFIG.M00_HAS_REGSLICE {1} \ # CONFIG.M01_HAS_REGSLICE {1} \ # CONFIG.M02_HAS_REGSLICE {1} \ # CONFIG.M03_HAS_REGSLICE {1} \ # CONFIG.M04_HAS_REGSLICE {1} \ # CONFIG.M05_HAS_REGSLICE {1} \ # CONFIG.M06_HAS_REGSLICE {1} \ # CONFIG.M07_HAS_REGSLICE {1} \ # CONFIG.NUM_MI {8} \ # CONFIG.S00_HAS_REGSLICE {1} \ # ] $microblaze_0_axi_periph # # # Create instance: rst_clk_wiz_1_100M, and set properties # set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] # set_property -dict [ list \ # CONFIG.C_AUX_RESET_HIGH {1} \ # ] $rst_clk_wiz_1_100M # # # Create instance: spi, and set properties # set spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 spi ] # set_property -dict [ list \ # CONFIG.C_USE_STARTUP {0} \ # ] $spi # # # Create instance: timer, and set properties # set timer [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 timer ] # # # Create interface connections # connect_bd_intf_net -intf_net BRAM_PORTB_1 [get_bd_intf_pins lmb/BRAM_PORTB] [get_bd_intf_pins mb_bram_ctrl/BRAM_PORTA] # connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI] # connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S_AXI] [get_bd_intf_pins mb_bram_ctrl/S_AXI] # connect_bd_intf_net -intf_net gpio_GPIO [get_bd_intf_pins gpio/GPIO] [get_bd_intf_pins io_switch/gpio] # connect_bd_intf_net -intf_net iic_IIC [get_bd_intf_pins iic/IIC] [get_bd_intf_pins io_switch/iic0] # connect_bd_intf_net -intf_net mb1_intc_interrupt [get_bd_intf_pins intc/interrupt] [get_bd_intf_pins mb/INTERRUPT] # connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins mb/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] [get_bd_intf_pins spi/AXI_LITE] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins iic/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins io_switch/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins gpio/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] [get_bd_intf_pins timer/S_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins intr/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI] # connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins DEBUG] [get_bd_intf_pins mb/DEBUG] # connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins lmb/DLMB] [get_bd_intf_pins mb/DLMB] # connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins lmb/ILMB] [get_bd_intf_pins mb/ILMB] # connect_bd_intf_net -intf_net spi_SPI_0 [get_bd_intf_pins io_switch/spi0] [get_bd_intf_pins spi/SPI_0] # # # Create port connections # connect_bd_net -net dff_en_reset_vector_0_q [get_bd_pins intr_req] [get_bd_pins dff_en_reset_vector_0/q] # connect_bd_net -net io_data_i_0_1 [get_bd_pins data_i] [get_bd_pins io_switch/io_data_i] # connect_bd_net -net io_switch_0_timer_i [get_bd_pins io_switch/timer_i] [get_bd_pins timer/capturetrig0] # connect_bd_net -net io_switch_io_data_o [get_bd_pins data_o] [get_bd_pins io_switch/io_data_o] # connect_bd_net -net io_switch_io_tri_o [get_bd_pins tri_o] [get_bd_pins io_switch/io_tri_o] # connect_bd_net -net iop_pmoda_intr_ack_1 [get_bd_pins intr_ack] [get_bd_pins dff_en_reset_vector_0/reset] # connect_bd_net -net iop_pmoda_intr_gpio_io_o [get_bd_pins dff_en_reset_vector_0/en] [get_bd_pins intr/gpio_io_o] # connect_bd_net -net logic_1_dout1 [get_bd_pins dff_en_reset_vector_0/d] [get_bd_pins logic_1/dout] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] # connect_bd_net -net mb1_iic_iic2intc_irpt [get_bd_pins iic/iic2intc_irpt] [get_bd_pins intr_concat/In0] # connect_bd_net -net mb1_interrupt_concat_dout [get_bd_pins intc/intr] [get_bd_pins intr_concat/dout] # connect_bd_net -net mb1_spi_ip2intc_irpt [get_bd_pins intr_concat/In1] [get_bd_pins spi/ip2intc_irpt] # connect_bd_net -net mb1_timer_generateout0 [get_bd_pins io_switch/timer_o] [get_bd_pins timer/generateout0] # connect_bd_net -net mb1_timer_interrupt [get_bd_pins intr_concat/In2] [get_bd_pins timer/interrupt] # connect_bd_net -net mb1_timer_pwm0 [get_bd_pins io_switch/pwm_o] [get_bd_pins timer/pwm0] # connect_bd_net -net mb_1_reset_Dout [get_bd_pins aux_reset_in] [get_bd_pins rst_clk_wiz_1_100M/aux_reset_in] # connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug_sys_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] # connect_bd_net -net ps7_0_FCLK_CLK0 [get_bd_pins clk_100M] [get_bd_pins dff_en_reset_vector_0/clk] [get_bd_pins gpio/s_axi_aclk] [get_bd_pins iic/s_axi_aclk] [get_bd_pins intc/s_axi_aclk] [get_bd_pins intr/s_axi_aclk] [get_bd_pins io_switch/s_axi_aclk] [get_bd_pins lmb/LMB_Clk] [get_bd_pins mb/Clk] [get_bd_pins mb_bram_ctrl/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] [get_bd_pins spi/ext_spi_clk] [get_bd_pins spi/s_axi_aclk] [get_bd_pins timer/s_axi_aclk] # connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins lmb/SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] # connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] # connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins mb/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] # connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins gpio/s_axi_aresetn] [get_bd_pins iic/s_axi_aresetn] [get_bd_pins intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] [get_bd_pins spi/s_axi_aresetn] [get_bd_pins timer/s_axi_aresetn] # connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins intr/s_axi_aresetn] [get_bd_pins io_switch/s_axi_aresetn] [get_bd_pins mb_bram_ctrl/s_axi_aresetn] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_hier_cell_iop_pmod0 { parentCell nameHier } { # # variable script_folder # # if { $parentCell eq "" || $nameHier eq "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_iop_pmod0() - Empty argument(s)!"} # return # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # Create cell and set as current instance # set hier_obj [create_bd_cell -type hier $nameHier] # current_bd_instance $hier_obj # # # Create interface pins # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:mbdebug_rtl:3.0 DEBUG # # create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI # # create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI # # # # Create pins # create_bd_pin -dir I -from 0 -to 0 -type rst aux_reset_in # create_bd_pin -dir I -type clk clk_100M # create_bd_pin -dir I -from 7 -to 0 data_i # create_bd_pin -dir O -from 7 -to 0 data_o # create_bd_pin -dir I -from 0 -to 0 intr_ack # create_bd_pin -dir O -from 0 -to 0 intr_req # create_bd_pin -dir I -type rst mb_debug_sys_rst # create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn # create_bd_pin -dir I -from 0 -to 0 -type rst s_axi_aresetn # create_bd_pin -dir O -from 7 -to 0 tri_o # # # Create instance: dff_en_reset_vector_0, and set properties # set dff_en_reset_vector_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:dff_en_reset_vector:1.0 dff_en_reset_vector_0 ] # set_property -dict [ list \ # CONFIG.SIZE {1} \ # ] $dff_en_reset_vector_0 # # # Create instance: gpio, and set properties # set gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio ] # set_property -dict [ list \ # CONFIG.C_ALL_OUTPUTS_2 {0} \ # CONFIG.C_GPIO2_WIDTH {32} \ # CONFIG.C_GPIO_WIDTH {8} \ # CONFIG.C_IS_DUAL {0} \ # ] $gpio # # # Create instance: iic, and set properties # set iic [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic ] # # # Create instance: intc, and set properties # set intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 intc ] # # # Create instance: intr, and set properties # set intr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 intr ] # set_property -dict [ list \ # CONFIG.C_ALL_OUTPUTS {1} \ # CONFIG.C_GPIO_WIDTH {1} \ # ] $intr # # # Create instance: intr_concat, and set properties # set intr_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat ] # set_property -dict [ list \ # CONFIG.NUM_PORTS {3} \ # ] $intr_concat # # # Create instance: io_switch, and set properties # set io_switch [ create_bd_cell -type ip -vlnv xilinx.com:user:io_switch:1.1 io_switch ] # set_property -dict [ list \ # CONFIG.C_INTERFACE_TYPE {1} \ # CONFIG.C_IO_SWITCH_WIDTH {8} \ # CONFIG.C_NUM_PWMS {1} \ # CONFIG.C_NUM_TIMERS {1} \ # CONFIG.I2C0_Enable {true} \ # CONFIG.PWM_Enable {true} \ # CONFIG.SPI0_Enable {true} \ # CONFIG.Timer_Enable {true} \ # ] $io_switch # # # Create instance: lmb # create_hier_cell_lmb $hier_obj lmb # # # Create instance: logic_1, and set properties # set logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 logic_1 ] # # # Create instance: mb, and set properties # set mb [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 mb ] # set_property -dict [ list \ # CONFIG.C_DEBUG_ENABLED {1} \ # CONFIG.C_D_AXI {1} \ # CONFIG.C_D_LMB {1} \ # CONFIG.C_I_LMB {1} \ # ] $mb # # # Create instance: mb_bram_ctrl, and set properties # set mb_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 mb_bram_ctrl ] # set_property -dict [ list \ # CONFIG.SINGLE_PORT_BRAM {1} \ # ] $mb_bram_ctrl # # # Create instance: microblaze_0_axi_periph, and set properties # set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] # set_property -dict [ list \ # CONFIG.M00_HAS_REGSLICE {1} \ # CONFIG.M01_HAS_REGSLICE {1} \ # CONFIG.M02_HAS_REGSLICE {1} \ # CONFIG.M03_HAS_REGSLICE {1} \ # CONFIG.M04_HAS_REGSLICE {1} \ # CONFIG.M05_HAS_REGSLICE {1} \ # CONFIG.M06_HAS_REGSLICE {1} \ # CONFIG.M07_HAS_REGSLICE {1} \ # CONFIG.NUM_MI {8} \ # CONFIG.S00_HAS_REGSLICE {1} \ # ] $microblaze_0_axi_periph # # # Create instance: rst_clk_wiz_1_100M, and set properties # set rst_clk_wiz_1_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_1_100M ] # set_property -dict [ list \ # CONFIG.C_AUX_RESET_HIGH {1} \ # ] $rst_clk_wiz_1_100M # # # Create instance: spi, and set properties # set spi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 spi ] # set_property -dict [ list \ # CONFIG.C_USE_STARTUP {0} \ # ] $spi # # # Create instance: timer, and set properties # set timer [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 timer ] # # # Create interface connections # connect_bd_intf_net -intf_net BRAM_PORTB_1 [get_bd_intf_pins lmb/BRAM_PORTB] [get_bd_intf_pins mb_bram_ctrl/BRAM_PORTA] # connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins M_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI] # connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins S_AXI] [get_bd_intf_pins mb_bram_ctrl/S_AXI] # connect_bd_intf_net -intf_net gpio_GPIO [get_bd_intf_pins gpio/GPIO] [get_bd_intf_pins io_switch/gpio] # connect_bd_intf_net -intf_net iic_IIC [get_bd_intf_pins iic/IIC] [get_bd_intf_pins io_switch/iic0] # connect_bd_intf_net -intf_net mb1_intc_interrupt [get_bd_intf_pins intc/interrupt] [get_bd_intf_pins mb/INTERRUPT] # connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins mb/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] [get_bd_intf_pins spi/AXI_LITE] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins iic/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins io_switch/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins gpio/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] [get_bd_intf_pins timer/S_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI] # connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins intr/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI] # connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins DEBUG] [get_bd_intf_pins mb/DEBUG] # connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins lmb/DLMB] [get_bd_intf_pins mb/DLMB] # connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins lmb/ILMB] [get_bd_intf_pins mb/ILMB] # connect_bd_intf_net -intf_net spi_SPI_0 [get_bd_intf_pins io_switch/spi0] [get_bd_intf_pins spi/SPI_0] # # # Create port connections # connect_bd_net -net dff_en_reset_vector_0_q [get_bd_pins intr_req] [get_bd_pins dff_en_reset_vector_0/q] # connect_bd_net -net io_data_i_0_1 [get_bd_pins data_i] [get_bd_pins io_switch/io_data_i] # connect_bd_net -net io_switch_0_timer_i [get_bd_pins io_switch/timer_i] [get_bd_pins timer/capturetrig0] # connect_bd_net -net io_switch_io_data_o [get_bd_pins data_o] [get_bd_pins io_switch/io_data_o] # connect_bd_net -net io_switch_io_tri_o [get_bd_pins tri_o] [get_bd_pins io_switch/io_tri_o] # connect_bd_net -net iop_pmoda_intr_ack_1 [get_bd_pins intr_ack] [get_bd_pins dff_en_reset_vector_0/reset] # connect_bd_net -net iop_pmoda_intr_gpio_io_o [get_bd_pins dff_en_reset_vector_0/en] [get_bd_pins intr/gpio_io_o] # connect_bd_net -net logic_1_dout1 [get_bd_pins dff_en_reset_vector_0/d] [get_bd_pins logic_1/dout] [get_bd_pins rst_clk_wiz_1_100M/ext_reset_in] # connect_bd_net -net mb1_iic_iic2intc_irpt [get_bd_pins iic/iic2intc_irpt] [get_bd_pins intr_concat/In0] # connect_bd_net -net mb1_interrupt_concat_dout [get_bd_pins intc/intr] [get_bd_pins intr_concat/dout] # connect_bd_net -net mb1_spi_ip2intc_irpt [get_bd_pins intr_concat/In1] [get_bd_pins spi/ip2intc_irpt] # connect_bd_net -net mb1_timer_generateout0 [get_bd_pins io_switch/timer_o] [get_bd_pins timer/generateout0] # connect_bd_net -net mb1_timer_interrupt [get_bd_pins intr_concat/In2] [get_bd_pins timer/interrupt] # connect_bd_net -net mb1_timer_pwm0 [get_bd_pins io_switch/pwm_o] [get_bd_pins timer/pwm0] # connect_bd_net -net mb_1_reset_Dout [get_bd_pins aux_reset_in] [get_bd_pins rst_clk_wiz_1_100M/aux_reset_in] # connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug_sys_rst] [get_bd_pins rst_clk_wiz_1_100M/mb_debug_sys_rst] # connect_bd_net -net ps7_0_FCLK_CLK0 [get_bd_pins clk_100M] [get_bd_pins dff_en_reset_vector_0/clk] [get_bd_pins gpio/s_axi_aclk] [get_bd_pins iic/s_axi_aclk] [get_bd_pins intc/s_axi_aclk] [get_bd_pins intr/s_axi_aclk] [get_bd_pins io_switch/s_axi_aclk] [get_bd_pins lmb/LMB_Clk] [get_bd_pins mb/Clk] [get_bd_pins mb_bram_ctrl/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins rst_clk_wiz_1_100M/slowest_sync_clk] [get_bd_pins spi/ext_spi_clk] [get_bd_pins spi/s_axi_aclk] [get_bd_pins timer/s_axi_aclk] # connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins lmb/SYS_Rst] [get_bd_pins rst_clk_wiz_1_100M/bus_struct_reset] # connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_1_100M/interconnect_aresetn] # connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins mb/Reset] [get_bd_pins rst_clk_wiz_1_100M/mb_reset] # connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins peripheral_aresetn] [get_bd_pins gpio/s_axi_aresetn] [get_bd_pins iic/s_axi_aresetn] [get_bd_pins intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_1_100M/peripheral_aresetn] [get_bd_pins spi/s_axi_aresetn] [get_bd_pins timer/s_axi_aresetn] # connect_bd_net -net s_axi_aresetn_1 [get_bd_pins s_axi_aresetn] [get_bd_pins intr/s_axi_aresetn] [get_bd_pins io_switch/s_axi_aresetn] [get_bd_pins mb_bram_ctrl/s_axi_aresetn] # # # Restore current instance # current_bd_instance $oldCurInst # } # proc create_root_design { parentCell } { # # variable script_folder # variable design_name # # if { $parentCell eq "" } { # set parentCell [get_bd_cells /] # } # # # Get object for parentCell # set parentObj [get_bd_cells $parentCell] # if { $parentObj == "" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} # return # } # # # Make sure parentObj is hier blk # set parentType [get_property TYPE $parentObj] # if { $parentType ne "hier" } { # catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} # return # } # # # Save current instance; Restore later # set oldCurInst [current_bd_instance .] # # # Set parent object as current # current_bd_instance $parentObj # # # # Create interface ports # set DRU_CLK_IN [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 DRU_CLK_IN ] # set_property -dict [ list \ # CONFIG.FREQ_HZ {156250000} \ # ] $DRU_CLK_IN # # set RX_DDC_OUT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 RX_DDC_OUT ] # # set TX_DDC_OUT [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 TX_DDC_OUT ] # # set dip_switch_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 dip_switch_4bits ] # # set fmch_iic [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 fmch_iic ] # # set led_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_4bits ] # # set push_button_4bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 push_button_4bits ] # # # # Create ports # set HDMI_RX_CLK_N_IN [ create_bd_port -dir I HDMI_RX_CLK_N_IN ] # set HDMI_RX_CLK_P_IN [ create_bd_port -dir I HDMI_RX_CLK_P_IN ] # set HDMI_RX_DAT_N_IN [ create_bd_port -dir I -from 2 -to 0 HDMI_RX_DAT_N_IN ] # set HDMI_RX_DAT_P_IN [ create_bd_port -dir I -from 2 -to 0 HDMI_RX_DAT_P_IN ] # set HDMI_RX_LS_OE [ create_bd_port -dir O -from 0 -to 0 HDMI_RX_LS_OE ] # set HDMI_TX_CLK_N_OUT [ create_bd_port -dir O HDMI_TX_CLK_N_OUT ] # set HDMI_TX_CLK_P_OUT [ create_bd_port -dir O HDMI_TX_CLK_P_OUT ] # set HDMI_TX_DAT_N_OUT [ create_bd_port -dir O -from 2 -to 0 HDMI_TX_DAT_N_OUT ] # set HDMI_TX_DAT_P_OUT [ create_bd_port -dir O -from 2 -to 0 HDMI_TX_DAT_P_OUT ] # set IDT_8T49N241_LOL_IN [ create_bd_port -dir I IDT_8T49N241_LOL_IN ] # set IDT_8T49N241_RST_OUT [ create_bd_port -dir O -from 0 -to 0 IDT_8T49N241_RST_OUT ] # set RX_DET_IN [ create_bd_port -dir I RX_DET_IN ] # set RX_HPD_OUT [ create_bd_port -dir O RX_HPD_OUT ] # set RX_REFCLK_N_OUT [ create_bd_port -dir O RX_REFCLK_N_OUT ] # set RX_REFCLK_P_OUT [ create_bd_port -dir O RX_REFCLK_P_OUT ] # set TX_EN_OUT [ create_bd_port -dir O -from 0 -to 0 TX_EN_OUT ] # set TX_HPD_IN [ create_bd_port -dir I TX_HPD_IN ] # set TX_REFCLK_N_IN [ create_bd_port -dir I TX_REFCLK_N_IN ] # set TX_REFCLK_P_IN [ create_bd_port -dir I TX_REFCLK_P_IN ] # set pmod0 [ create_bd_port -dir IO -from 7 -to 0 pmod0 ] # set pmod1 [ create_bd_port -dir IO -from 7 -to 0 pmod1 ] # set reset [ create_bd_port -dir I -type rst reset ] # set_property -dict [ list \ # CONFIG.POLARITY {ACTIVE_HIGH} \ # ] $reset # # # Create instance: address_remap_0, and set properties # set address_remap_0 [ create_bd_cell -type ip -vlnv user.org:user:address_remap:1.0 address_remap_0 ] # set_property -dict [ list \ # CONFIG.C_M_AXI_out_ADDR_WIDTH {31} \ # CONFIG.C_M_AXI_out_DATA_WIDTH {128} \ # CONFIG.C_S_AXI_in_ADDR_WIDTH {31} \ # CONFIG.C_S_AXI_in_DATA_WIDTH {128} \ # ] $address_remap_0 # # # Create instance: axi_intc_0, and set properties # set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] # set_property -dict [ list \ # CONFIG.C_IRQ_CONNECTION {1} \ # ] $axi_intc_0 # # # Create instance: axi_interconnect, and set properties # set axi_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect ] # set_property -dict [ list \ # CONFIG.NUM_MI {19} \ # ] $axi_interconnect # # # Create instance: axi_interconnect_0, and set properties # set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] # set_property -dict [ list \ # CONFIG.NUM_MI {1} \ # CONFIG.NUM_SI {2} \ # ] $axi_interconnect_0 # # # Create instance: axi_mem_intercon, and set properties # set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] # set_property -dict [ list \ # CONFIG.NUM_MI {1} \ # ] $axi_mem_intercon # # # Create instance: axi_mem_intercon_1, and set properties # set axi_mem_intercon_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon_1 ] # set_property -dict [ list \ # CONFIG.NUM_MI {1} \ # ] $axi_mem_intercon_1 # # # Create instance: fmch_axi_iic, and set properties # set fmch_axi_iic [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 fmch_axi_iic ] # set_property -dict [ list \ # CONFIG.C_SCL_INERTIAL_DELAY {10} \ # CONFIG.C_SDA_INERTIAL_DELAY {10} \ # CONFIG.IIC_BOARD_INTERFACE {Custom} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $fmch_axi_iic # # # Create instance: gpio_btns, and set properties # set gpio_btns [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_btns ] # set_property -dict [ list \ # CONFIG.C_INTERRUPT_PRESENT {1} \ # CONFIG.GPIO_BOARD_INTERFACE {push_button_4bits} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $gpio_btns # # # Create instance: gpio_leds, and set properties # set gpio_leds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_leds ] # set_property -dict [ list \ # CONFIG.C_INTERRUPT_PRESENT {0} \ # CONFIG.GPIO_BOARD_INTERFACE {led_4bits} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $gpio_leds # # # Create instance: gpio_sws, and set properties # set gpio_sws [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_sws ] # set_property -dict [ list \ # CONFIG.C_INTERRUPT_PRESENT {1} \ # CONFIG.GPIO_BOARD_INTERFACE {dip_switch_4bits} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $gpio_sws # # # Create instance: iop_pmod0 # create_hier_cell_iop_pmod0 [current_bd_instance .] iop_pmod0 # # # Create instance: iop_pmod1 # create_hier_cell_iop_pmod1 [current_bd_instance .] iop_pmod1 # # # Create instance: mb_iop_pmod0_intr_ack, and set properties # set mb_iop_pmod0_intr_ack [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 mb_iop_pmod0_intr_ack ] # set_property -dict [ list \ # CONFIG.DIN_FROM {1} \ # CONFIG.DIN_TO {1} \ # CONFIG.DIN_WIDTH {4} \ # CONFIG.DOUT_WIDTH {1} \ # ] $mb_iop_pmod0_intr_ack # # # Create instance: mb_iop_pmod0_reset, and set properties # set mb_iop_pmod0_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 mb_iop_pmod0_reset ] # set_property -dict [ list \ # CONFIG.DIN_FROM {0} \ # CONFIG.DIN_TO {0} \ # CONFIG.DIN_WIDTH {4} \ # ] $mb_iop_pmod0_reset # # # Create instance: mb_iop_pmod1_intr_ack, and set properties # set mb_iop_pmod1_intr_ack [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 mb_iop_pmod1_intr_ack ] # set_property -dict [ list \ # CONFIG.DIN_FROM {3} \ # CONFIG.DIN_TO {3} \ # CONFIG.DIN_WIDTH {4} \ # CONFIG.DOUT_WIDTH {1} \ # ] $mb_iop_pmod1_intr_ack # # # Create instance: mb_iop_pmod1_reset, and set properties # set mb_iop_pmod1_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 mb_iop_pmod1_reset ] # set_property -dict [ list \ # CONFIG.DIN_FROM {2} \ # CONFIG.DIN_TO {2} \ # CONFIG.DIN_WIDTH {4} \ # CONFIG.DOUT_WIDTH {1} \ # ] $mb_iop_pmod1_reset # # # Create instance: mdm, and set properties # set mdm [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm ] # set_property -dict [ list \ # CONFIG.C_MB_DBG_PORTS {2} \ # ] $mdm # # # Create instance: pmod0_buf, and set properties # set pmod0_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 pmod0_buf ] # set_property -dict [ list \ # CONFIG.C_BUF_TYPE {IOBUF} \ # CONFIG.C_SIZE {8} \ # ] $pmod0_buf # # # Create instance: pmod1_buf, and set properties # set pmod1_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 pmod1_buf ] # set_property -dict [ list \ # CONFIG.C_BUF_TYPE {IOBUF} \ # CONFIG.C_SIZE {8} \ # ] $pmod1_buf # # # Create instance: proc_sys_reset_0, and set properties # set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] # set_property -dict [ list \ # CONFIG.RESET_BOARD_INTERFACE {reset} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $proc_sys_reset_0 # # # Create instance: proc_sys_reset_1, and set properties # set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] # set_property -dict [ list \ # CONFIG.RESET_BOARD_INTERFACE {reset} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $proc_sys_reset_1 # # # Create instance: proc_sys_reset_2, and set properties # set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ] # set_property -dict [ list \ # CONFIG.RESET_BOARD_INTERFACE {reset} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $proc_sys_reset_2 # # # Create instance: proc_sys_reset_3, and set properties # set proc_sys_reset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_3 ] # set_property -dict [ list \ # CONFIG.RESET_BOARD_INTERFACE {reset} \ # CONFIG.USE_BOARD_FLOW {true} \ # ] $proc_sys_reset_3 # # # Create instance: ps_e_0, and set properties # set ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 ps_e_0 ] # set_property -dict [ list \ # CONFIG.CAN0_BOARD_INTERFACE {custom} \ # CONFIG.CAN1_BOARD_INTERFACE {custom} \ # CONFIG.CSU_BOARD_INTERFACE {custom} \ # CONFIG.DP_BOARD_INTERFACE {custom} \ # CONFIG.GEM0_BOARD_INTERFACE {custom} \ # CONFIG.GEM1_BOARD_INTERFACE {custom} \ # CONFIG.GEM2_BOARD_INTERFACE {custom} \ # CONFIG.GEM3_BOARD_INTERFACE {custom} \ # CONFIG.GPIO_BOARD_INTERFACE {custom} \ # CONFIG.IIC0_BOARD_INTERFACE {custom} \ # CONFIG.IIC1_BOARD_INTERFACE {custom} \ # CONFIG.NAND_BOARD_INTERFACE {custom} \ # CONFIG.PCIE_BOARD_INTERFACE {custom} \ # CONFIG.PJTAG_BOARD_INTERFACE {custom} \ # CONFIG.PMU_BOARD_INTERFACE {custom} \ # CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ # CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ # CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ # CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \ # CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ # CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ # CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ # CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ # CONFIG.PSU_IMPORT_BOARD_PRESET {} \ # CONFIG.PSU_MIO_0_DIRECTION {out} \ # CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_0_POLARITY {Default} \ # CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_0_SLEW {slow} \ # CONFIG.PSU_MIO_10_DIRECTION {inout} \ # CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_10_POLARITY {Default} \ # CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_10_SLEW {slow} \ # CONFIG.PSU_MIO_11_DIRECTION {inout} \ # CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_11_POLARITY {Default} \ # CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_11_SLEW {slow} \ # CONFIG.PSU_MIO_12_DIRECTION {inout} \ # CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_12_POLARITY {Default} \ # CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_12_SLEW {slow} \ # CONFIG.PSU_MIO_13_DIRECTION {inout} \ # CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_13_POLARITY {Default} \ # CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_13_SLEW {slow} \ # CONFIG.PSU_MIO_14_DIRECTION {inout} \ # CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_14_POLARITY {Default} \ # CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_14_SLEW {slow} \ # CONFIG.PSU_MIO_15_DIRECTION {inout} \ # CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_15_POLARITY {Default} \ # CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_15_SLEW {slow} \ # CONFIG.PSU_MIO_16_DIRECTION {inout} \ # CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_16_POLARITY {Default} \ # CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_16_SLEW {slow} \ # CONFIG.PSU_MIO_17_DIRECTION {inout} \ # CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_17_POLARITY {Default} \ # CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_17_SLEW {slow} \ # CONFIG.PSU_MIO_18_DIRECTION {in} \ # CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_18_POLARITY {Default} \ # CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_18_SLEW {fast} \ # CONFIG.PSU_MIO_19_DIRECTION {out} \ # CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_19_POLARITY {Default} \ # CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_19_SLEW {slow} \ # CONFIG.PSU_MIO_1_DIRECTION {inout} \ # CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_1_POLARITY {Default} \ # CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_1_SLEW {slow} \ # CONFIG.PSU_MIO_20_DIRECTION {out} \ # CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_20_POLARITY {Default} \ # CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_20_SLEW {slow} \ # CONFIG.PSU_MIO_21_DIRECTION {in} \ # CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_21_POLARITY {Default} \ # CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_21_SLEW {fast} \ # CONFIG.PSU_MIO_22_DIRECTION {inout} \ # CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_22_POLARITY {Default} \ # CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_22_SLEW {slow} \ # CONFIG.PSU_MIO_23_DIRECTION {inout} \ # CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_23_POLARITY {Default} \ # CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_23_SLEW {slow} \ # CONFIG.PSU_MIO_24_DIRECTION {out} \ # CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_24_POLARITY {Default} \ # CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_24_SLEW {slow} \ # CONFIG.PSU_MIO_25_DIRECTION {in} \ # CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_25_POLARITY {Default} \ # CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_25_SLEW {fast} \ # CONFIG.PSU_MIO_26_DIRECTION {inout} \ # CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_26_POLARITY {Default} \ # CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_26_SLEW {slow} \ # CONFIG.PSU_MIO_27_DIRECTION {out} \ # CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_27_POLARITY {Default} \ # CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_27_SLEW {slow} \ # CONFIG.PSU_MIO_28_DIRECTION {in} \ # CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_28_POLARITY {Default} \ # CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_28_SLEW {fast} \ # CONFIG.PSU_MIO_29_DIRECTION {out} \ # CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_29_POLARITY {Default} \ # CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_29_SLEW {slow} \ # CONFIG.PSU_MIO_2_DIRECTION {inout} \ # CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_2_POLARITY {Default} \ # CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_2_SLEW {slow} \ # CONFIG.PSU_MIO_30_DIRECTION {in} \ # CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_30_POLARITY {Default} \ # CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_30_SLEW {fast} \ # CONFIG.PSU_MIO_31_DIRECTION {inout} \ # CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_31_POLARITY {Default} \ # CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_31_SLEW {slow} \ # CONFIG.PSU_MIO_32_DIRECTION {inout} \ # CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_32_POLARITY {Default} \ # CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_32_SLEW {slow} \ # CONFIG.PSU_MIO_33_DIRECTION {inout} \ # CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_33_POLARITY {Default} \ # CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_33_SLEW {slow} \ # CONFIG.PSU_MIO_34_DIRECTION {inout} \ # CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_34_POLARITY {Default} \ # CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_34_SLEW {slow} \ # CONFIG.PSU_MIO_35_DIRECTION {inout} \ # CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_35_POLARITY {Default} \ # CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_35_SLEW {slow} \ # CONFIG.PSU_MIO_36_DIRECTION {inout} \ # CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_36_POLARITY {Default} \ # CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_36_SLEW {slow} \ # CONFIG.PSU_MIO_37_DIRECTION {inout} \ # CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_37_POLARITY {Default} \ # CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_37_SLEW {slow} \ # CONFIG.PSU_MIO_38_DIRECTION {inout} \ # CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_38_POLARITY {Default} \ # CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_38_SLEW {slow} \ # CONFIG.PSU_MIO_39_DIRECTION {inout} \ # CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_39_POLARITY {Default} \ # CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_39_SLEW {slow} \ # CONFIG.PSU_MIO_3_DIRECTION {inout} \ # CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_3_POLARITY {Default} \ # CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_3_SLEW {slow} \ # CONFIG.PSU_MIO_40_DIRECTION {inout} \ # CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_40_POLARITY {Default} \ # CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_40_SLEW {slow} \ # CONFIG.PSU_MIO_41_DIRECTION {inout} \ # CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_41_POLARITY {Default} \ # CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_41_SLEW {slow} \ # CONFIG.PSU_MIO_42_DIRECTION {inout} \ # CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_42_POLARITY {Default} \ # CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_42_SLEW {slow} \ # CONFIG.PSU_MIO_43_DIRECTION {inout} \ # CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_43_POLARITY {Default} \ # CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_43_SLEW {slow} \ # CONFIG.PSU_MIO_44_DIRECTION {inout} \ # CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_44_POLARITY {Default} \ # CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_44_SLEW {slow} \ # CONFIG.PSU_MIO_45_DIRECTION {in} \ # CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_45_POLARITY {Default} \ # CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_45_SLEW {fast} \ # CONFIG.PSU_MIO_46_DIRECTION {inout} \ # CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_46_POLARITY {Default} \ # CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_46_SLEW {slow} \ # CONFIG.PSU_MIO_47_DIRECTION {inout} \ # CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_47_POLARITY {Default} \ # CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_47_SLEW {slow} \ # CONFIG.PSU_MIO_48_DIRECTION {inout} \ # CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_48_POLARITY {Default} \ # CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_48_SLEW {slow} \ # CONFIG.PSU_MIO_49_DIRECTION {inout} \ # CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_49_POLARITY {Default} \ # CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_49_SLEW {slow} \ # CONFIG.PSU_MIO_4_DIRECTION {inout} \ # CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_4_POLARITY {Default} \ # CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_4_SLEW {slow} \ # CONFIG.PSU_MIO_50_DIRECTION {inout} \ # CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_50_POLARITY {Default} \ # CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_50_SLEW {slow} \ # CONFIG.PSU_MIO_51_DIRECTION {out} \ # CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_51_POLARITY {Default} \ # CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_51_SLEW {slow} \ # CONFIG.PSU_MIO_52_DIRECTION {in} \ # CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_52_POLARITY {Default} \ # CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_52_SLEW {fast} \ # CONFIG.PSU_MIO_53_DIRECTION {in} \ # CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_53_POLARITY {Default} \ # CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_53_SLEW {fast} \ # CONFIG.PSU_MIO_54_DIRECTION {inout} \ # CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_54_POLARITY {Default} \ # CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_54_SLEW {slow} \ # CONFIG.PSU_MIO_55_DIRECTION {in} \ # CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_55_POLARITY {Default} \ # CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_55_SLEW {fast} \ # CONFIG.PSU_MIO_56_DIRECTION {inout} \ # CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_56_POLARITY {Default} \ # CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_56_SLEW {slow} \ # CONFIG.PSU_MIO_57_DIRECTION {inout} \ # CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_57_POLARITY {Default} \ # CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_57_SLEW {slow} \ # CONFIG.PSU_MIO_58_DIRECTION {out} \ # CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_58_POLARITY {Default} \ # CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_58_SLEW {slow} \ # CONFIG.PSU_MIO_59_DIRECTION {inout} \ # CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_59_POLARITY {Default} \ # CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_59_SLEW {slow} \ # CONFIG.PSU_MIO_5_DIRECTION {out} \ # CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_5_POLARITY {Default} \ # CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_5_SLEW {slow} \ # CONFIG.PSU_MIO_60_DIRECTION {inout} \ # CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_60_POLARITY {Default} \ # CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_60_SLEW {slow} \ # CONFIG.PSU_MIO_61_DIRECTION {inout} \ # CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_61_POLARITY {Default} \ # CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_61_SLEW {slow} \ # CONFIG.PSU_MIO_62_DIRECTION {inout} \ # CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_62_POLARITY {Default} \ # CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_62_SLEW {slow} \ # CONFIG.PSU_MIO_63_DIRECTION {inout} \ # CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_63_POLARITY {Default} \ # CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_63_SLEW {slow} \ # CONFIG.PSU_MIO_64_DIRECTION {out} \ # CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_64_POLARITY {Default} \ # CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_64_SLEW {slow} \ # CONFIG.PSU_MIO_65_DIRECTION {out} \ # CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_65_POLARITY {Default} \ # CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_65_SLEW {slow} \ # CONFIG.PSU_MIO_66_DIRECTION {out} \ # CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_66_POLARITY {Default} \ # CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_66_SLEW {slow} \ # CONFIG.PSU_MIO_67_DIRECTION {out} \ # CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_67_POLARITY {Default} \ # CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_67_SLEW {slow} \ # CONFIG.PSU_MIO_68_DIRECTION {out} \ # CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_68_POLARITY {Default} \ # CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_68_SLEW {slow} \ # CONFIG.PSU_MIO_69_DIRECTION {out} \ # CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_69_POLARITY {Default} \ # CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_69_SLEW {slow} \ # CONFIG.PSU_MIO_6_DIRECTION {out} \ # CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_6_POLARITY {Default} \ # CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_6_SLEW {slow} \ # CONFIG.PSU_MIO_70_DIRECTION {in} \ # CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_70_POLARITY {Default} \ # CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_70_SLEW {fast} \ # CONFIG.PSU_MIO_71_DIRECTION {in} \ # CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_71_POLARITY {Default} \ # CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_71_SLEW {fast} \ # CONFIG.PSU_MIO_72_DIRECTION {in} \ # CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_72_POLARITY {Default} \ # CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_72_SLEW {fast} \ # CONFIG.PSU_MIO_73_DIRECTION {in} \ # CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_73_POLARITY {Default} \ # CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_73_SLEW {fast} \ # CONFIG.PSU_MIO_74_DIRECTION {in} \ # CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_74_POLARITY {Default} \ # CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_74_SLEW {fast} \ # CONFIG.PSU_MIO_75_DIRECTION {in} \ # CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_75_POLARITY {Default} \ # CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_75_SLEW {fast} \ # CONFIG.PSU_MIO_76_DIRECTION {out} \ # CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ # CONFIG.PSU_MIO_76_POLARITY {Default} \ # CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_76_SLEW {slow} \ # CONFIG.PSU_MIO_77_DIRECTION {inout} \ # CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_77_POLARITY {Default} \ # CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_77_SLEW {slow} \ # CONFIG.PSU_MIO_7_DIRECTION {inout} \ # CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_7_POLARITY {Default} \ # CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_7_SLEW {slow} \ # CONFIG.PSU_MIO_8_DIRECTION {inout} \ # CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_8_POLARITY {Default} \ # CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_8_SLEW {slow} \ # CONFIG.PSU_MIO_9_DIRECTION {inout} \ # CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ # CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ # CONFIG.PSU_MIO_9_POLARITY {Default} \ # CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ # CONFIG.PSU_MIO_9_SLEW {slow} \ # CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#CAN 1#CAN 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ # CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#gpio0[7]#gpio0[8]#gpio0[9]#gpio0[10]#gpio0[11]#gpio0[12]#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#phy_tx#phy_rx#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpio1[32]#gpio1[33]#gpio1[34]#gpio1[35]#gpio1[36]#gpio1[37]#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ # CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ # CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ # CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ # CONFIG.PSU_SMC_CYCLE_T0 {NA} \ # CONFIG.PSU_SMC_CYCLE_T1 {NA} \ # CONFIG.PSU_SMC_CYCLE_T2 {NA} \ # CONFIG.PSU_SMC_CYCLE_T3 {NA} \ # CONFIG.PSU_SMC_CYCLE_T4 {NA} \ # CONFIG.PSU_SMC_CYCLE_T5 {NA} \ # CONFIG.PSU_SMC_CYCLE_T6 {NA} \ # CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \ # CONFIG.PSU_VALUE_SILVERSION {3} \ # CONFIG.PSU__ACPU0__POWER__ON {1} \ # CONFIG.PSU__ACPU1__POWER__ON {1} \ # CONFIG.PSU__ACPU2__POWER__ON {1} \ # CONFIG.PSU__ACPU3__POWER__ON {1} \ # CONFIG.PSU__ACTUAL__IP {1} \ # CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ # CONFIG.PSU__AFI0_COHERENCY {0} \ # CONFIG.PSU__AFI1_COHERENCY {0} \ # CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ # CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ # CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ # CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ # CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \ # CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.988037} \ # CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ # CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ # CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ # CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ # CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ # CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ # CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ # CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ # CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ # CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ # CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ # CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ # CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ # CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ # CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ # CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ # CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {533.328003} \ # CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \ # CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ # CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ # CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ # CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ # CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ # CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ # CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ # CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ # CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ # CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.999750} \ # CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {20} \ # CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ # CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ # CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.315527} \ # CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {19} \ # CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ # CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {299.997009} \ # CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ # CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ # CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ # CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ # CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.994019} \ # CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ # CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ # CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.994995} \ # CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ # CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ # CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ # CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ # CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ # CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ # CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ # CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.328003} \ # CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ # CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ # CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ # CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ # CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ # CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ # CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ # CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ # CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ # CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.994995} \ # CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ # CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {49.999500} \ # CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ # CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ # CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.994995} \ # CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ # CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ # CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ # CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ # CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ # CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.984985} \ # CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ # CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ # CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ # CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ # CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {124.998749} \ # CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ # CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ # CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ # CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ # CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ # CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ # CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ # CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.994995} \ # CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ # CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.498123} \ # CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ # CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {299.997009} \ # CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {5} \ # CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {300} \ # CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {149.998505} \ # CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {10} \ # CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {150} \ # CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {124.998749} \ # CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \ # CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ # CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ # CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {90} \ # CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ # CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ # CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ # CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ # CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ # CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \ # CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.498123} \ # CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ # CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \ # CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \ # CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \ # CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \ # CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ # CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \ # CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ # CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ # CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.997498} \ # CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ # CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ # CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ # CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {19.999800} \ # CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ # CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ # CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ # CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ # CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ # CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \ # CONFIG.PSU__CSU_COHERENCY {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ # CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ # CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__DDRC__ADDR_MIRROR {0} \ # CONFIG.PSU__DDRC__AL {0} \ # CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \ # CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \ # CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ # CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \ # CONFIG.PSU__DDRC__CL {15} \ # CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ # CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ # CONFIG.PSU__DDRC__COMPONENTS {Components} \ # CONFIG.PSU__DDRC__CWL {14} \ # CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \ # CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \ # CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \ # CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \ # CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \ # CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \ # CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \ # CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \ # CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ # CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \ # CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ # CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ # CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ # CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ # CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ # CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ # CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ # CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ # CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ # CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ # CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ # CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ # CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ # CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ # CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ # CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ # CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ # CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ # CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ # CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ # CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \ # CONFIG.PSU__DDRC__ECC {Disabled} \ # CONFIG.PSU__DDRC__ECC_SCRUB {0} \ # CONFIG.PSU__DDRC__ENABLE {1} \ # CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ # CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ # CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ # CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ # CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ # CONFIG.PSU__DDRC__FGRM {1X} \ # CONFIG.PSU__DDRC__FREQ_MHZ {1} \ # CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ # CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \ # CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \ # CONFIG.PSU__DDRC__LP_ASR {manual normal} \ # CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \ # CONFIG.PSU__DDRC__PARITY_ENABLE {0} \ # CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ # CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ # CONFIG.PSU__DDRC__PLL_BYPASS {0} \ # CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ # CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ # CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ # CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ # CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \ # CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \ # CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \ # CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ # CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ # CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ # CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ # CONFIG.PSU__DDRC__T_FAW {30.0} \ # CONFIG.PSU__DDRC__T_RAS_MIN {33} \ # CONFIG.PSU__DDRC__T_RC {47.06} \ # CONFIG.PSU__DDRC__T_RCD {15} \ # CONFIG.PSU__DDRC__T_RP {15} \ # CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ # CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ # CONFIG.PSU__DDRC__VREF {1} \ # CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ # CONFIG.PSU__DDR_QOS_ENABLE {0} \ # CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \ # CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \ # CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \ # CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \ # CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \ # CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \ # CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \ # CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \ # CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \ # CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \ # CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \ # CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \ # CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \ # CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ # CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \ # CONFIG.PSU__DEVICE_TYPE {EV} \ # CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ # CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ # CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ # CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ # CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__DLL__ISUSED {1} \ # CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ # CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ # CONFIG.PSU__DP__REF_CLK_FREQ {27} \ # CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \ # CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ # CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ # CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ # CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__ENET0__PTP__ENABLE {0} \ # CONFIG.PSU__ENET0__TSU__ENABLE {0} \ # CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ # CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ # CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__ENET1__PTP__ENABLE {0} \ # CONFIG.PSU__ENET1__TSU__ENABLE {0} \ # CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ # CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ # CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__ENET2__PTP__ENABLE {0} \ # CONFIG.PSU__ENET2__TSU__ENABLE {0} \ # CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ # CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \ # CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \ # CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \ # CONFIG.PSU__ENET3__PTP__ENABLE {0} \ # CONFIG.PSU__ENET3__TSU__ENABLE {0} \ # CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ # CONFIG.PSU__EN_EMIO_TRACE {0} \ # CONFIG.PSU__EP__IP {0} \ # CONFIG.PSU__EXPAND__CORESIGHT {0} \ # CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ # CONFIG.PSU__EXPAND__GIC {0} \ # CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ # CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ # CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ # CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {99.999001} \ # CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ # CONFIG.PSU__FPGA_PL0_ENABLE {1} \ # CONFIG.PSU__FPGA_PL1_ENABLE {1} \ # CONFIG.PSU__FPGA_PL2_ENABLE {1} \ # CONFIG.PSU__FPGA_PL3_ENABLE {1} \ # CONFIG.PSU__FP__POWER__ON {1} \ # CONFIG.PSU__FTM__CTI_IN_0 {0} \ # CONFIG.PSU__FTM__CTI_IN_1 {0} \ # CONFIG.PSU__FTM__CTI_IN_2 {0} \ # CONFIG.PSU__FTM__CTI_IN_3 {0} \ # CONFIG.PSU__FTM__CTI_OUT_0 {0} \ # CONFIG.PSU__FTM__CTI_OUT_1 {0} \ # CONFIG.PSU__FTM__CTI_OUT_2 {0} \ # CONFIG.PSU__FTM__CTI_OUT_3 {0} \ # CONFIG.PSU__FTM__GPI {0} \ # CONFIG.PSU__FTM__GPO {0} \ # CONFIG.PSU__GEM0_COHERENCY {0} \ # CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__GEM1_COHERENCY {0} \ # CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__GEM2_COHERENCY {0} \ # CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__GEM3_COHERENCY {0} \ # CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__GEM__TSU__ENABLE {0} \ # CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ # CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ # CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ # CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ # CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ # CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ # CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ # CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ # CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ # CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ # CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ # CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ # CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ # CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ # CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ # CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ # CONFIG.PSU__GPU_PP0__POWER__ON {1} \ # CONFIG.PSU__GPU_PP1__POWER__ON {1} \ # CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ # CONFIG.PSU__GT__LINK_SPEED {HBR} \ # CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ # CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ # CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \ # CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ # CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ # CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ # CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ # CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ # CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ # CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ # CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ # CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ # CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ # CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ # CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ # CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ # CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ # CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ # CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ # CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.999001} \ # CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.999001} \ # CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ # CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ # CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ # CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ # CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ # CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ # CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ # CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ # CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ # CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ # CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ # CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ # CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ # CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ # CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ # CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ # CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ # CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ # CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ # CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ # CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ # CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ # CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ # CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ # CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ # CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ # CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ # CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ # CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ # CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ # CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ # CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ # CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ # CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ # CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ # CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ # CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ # CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ # CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ # CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ # CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ # CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ # CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ # CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ # CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ # CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ # CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ # CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ # CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ # CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ # CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ # CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ # CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ # CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ # CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ # CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ # CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ # CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ # CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ # CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ # CONFIG.PSU__L2_BANK0__POWER__ON {1} \ # CONFIG.PSU__LPDMA0_COHERENCY {0} \ # CONFIG.PSU__LPDMA1_COHERENCY {0} \ # CONFIG.PSU__LPDMA2_COHERENCY {0} \ # CONFIG.PSU__LPDMA3_COHERENCY {0} \ # CONFIG.PSU__LPDMA4_COHERENCY {0} \ # CONFIG.PSU__LPDMA5_COHERENCY {0} \ # CONFIG.PSU__LPDMA6_COHERENCY {0} \ # CONFIG.PSU__LPDMA7_COHERENCY {0} \ # CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ # CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \ # CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \ # CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ # CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ # CONFIG.PSU__MAXIGP2__DATA_WIDTH {128} \ # CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ # CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ # CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ # CONFIG.PSU__NAND_COHERENCY {0} \ # CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ # CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ # CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ # CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ # CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ # CONFIG.PSU__NUM_FABRIC_RESETS {1} \ # CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ # CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ # CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ # CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ # CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ # CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ # CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ # CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ # CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ # CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ # CONFIG.PSU__PCIE__BAR0_64BIT {0} \ # CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR0_VAL {} \ # CONFIG.PSU__PCIE__BAR1_64BIT {0} \ # CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR1_VAL {} \ # CONFIG.PSU__PCIE__BAR2_64BIT {0} \ # CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR2_VAL {} \ # CONFIG.PSU__PCIE__BAR3_64BIT {0} \ # CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR3_VAL {} \ # CONFIG.PSU__PCIE__BAR4_64BIT {0} \ # CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR4_VAL {} \ # CONFIG.PSU__PCIE__BAR5_64BIT {0} \ # CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ # CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ # CONFIG.PSU__PCIE__BAR5_VAL {} \ # CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ # CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ # CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ # CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ # CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ # CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ # CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ # CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ # CONFIG.PSU__PCIE__DEVICE_ID {} \ # CONFIG.PSU__PCIE__ECRC_CHECK {0} \ # CONFIG.PSU__PCIE__ECRC_ERR {0} \ # CONFIG.PSU__PCIE__ECRC_GEN {0} \ # CONFIG.PSU__PCIE__EROM_ENABLE {0} \ # CONFIG.PSU__PCIE__EROM_VAL {} \ # CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ # CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ # CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ # CONFIG.PSU__PCIE__INTX_GENERATION {0} \ # CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ # CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ # CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ # CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ # CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ # CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ # CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ # CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ # CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ # CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ # CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ # CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ # CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ # CONFIG.PSU__PCIE__MULTIHEADER {0} \ # CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ # CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ # CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ # CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ # CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ # CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ # CONFIG.PSU__PCIE__REVISION_ID {} \ # CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ # CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ # CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ # CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ # CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ # CONFIG.PSU__PCIE__VENDOR_ID {} \ # CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__PL_CLK0_BUF {TRUE} \ # CONFIG.PSU__PL_CLK1_BUF {TRUE} \ # CONFIG.PSU__PL_CLK2_BUF {TRUE} \ # CONFIG.PSU__PL_CLK3_BUF {TRUE} \ # CONFIG.PSU__PL__POWER__ON {1} \ # CONFIG.PSU__PMU_COHERENCY {0} \ # CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ # CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ # CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ # CONFIG.PSU__PMU__GPI0__ENABLE {0} \ # CONFIG.PSU__PMU__GPI1__ENABLE {0} \ # CONFIG.PSU__PMU__GPI2__ENABLE {0} \ # CONFIG.PSU__PMU__GPI3__ENABLE {0} \ # CONFIG.PSU__PMU__GPI4__ENABLE {0} \ # CONFIG.PSU__PMU__GPI5__ENABLE {0} \ # CONFIG.PSU__PMU__GPO0__ENABLE {0} \ # CONFIG.PSU__PMU__GPO1__ENABLE {0} \ # CONFIG.PSU__PMU__GPO2__ENABLE {0} \ # CONFIG.PSU__PMU__GPO3__ENABLE {0} \ # CONFIG.PSU__PMU__GPO4__ENABLE {0} \ # CONFIG.PSU__PMU__GPO5__ENABLE {0} \ # CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ # CONFIG.PSU__PRESET_APPLIED {1} \ # CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ # CONFIG.PSU__PROTECTION__DEBUG {0} \ # CONFIG.PSU__PROTECTION__ENABLE {0} \ # CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ # CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ # CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ # CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;1|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ # CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ # CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ # CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ # CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ # CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \ # CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ # CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ # CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ # CONFIG.PSU__QSPI_COHERENCY {0} \ # CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ # CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ # CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ # CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \ # CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \ # CONFIG.PSU__REPORT__DBGLOG {0} \ # CONFIG.PSU__RPU_COHERENCY {0} \ # CONFIG.PSU__RPU__POWER__ON {1} \ # CONFIG.PSU__SATA__LANE0__ENABLE {0} \ # CONFIG.PSU__SATA__LANE1__ENABLE {1} \ # CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \ # CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__SATA__REF_CLK_FREQ {125} \ # CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \ # CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ # CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ # CONFIG.PSU__SD0_COHERENCY {0} \ # CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \ # CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ # CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ # CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__SD0__RESET__ENABLE {0} \ # CONFIG.PSU__SD1_COHERENCY {0} \ # CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \ # CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \ # CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \ # CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \ # CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ # CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ # CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \ # CONFIG.PSU__SD1__RESET__ENABLE {0} \ # CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \ # CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ # CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ # CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ # CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ # CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ # CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ # CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ # CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ # CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ # CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ # CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ # CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ # CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ # CONFIG.PSU__TCM0A__POWER__ON {1} \ # CONFIG.PSU__TCM0B__POWER__ON {1} \ # CONFIG.PSU__TCM1A__POWER__ON {1} \ # CONFIG.PSU__TCM1B__POWER__ON {1} \ # CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ # CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ # CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__TRISTATE__INVERTED {1} \ # CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ # CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ # CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ # CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ # CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ # CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ # CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ # CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ # CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ # CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ # CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ # CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ # CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ # CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ # CONFIG.PSU__UART0__BAUD_RATE {115200} \ # CONFIG.PSU__UART0__MODEM__ENABLE {0} \ # CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \ # CONFIG.PSU__UART1__BAUD_RATE {115200} \ # CONFIG.PSU__UART1__MODEM__ENABLE {0} \ # CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \ # CONFIG.PSU__USB0_COHERENCY {0} \ # CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ # CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ # CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \ # CONFIG.PSU__USB0__RESET__ENABLE {0} \ # CONFIG.PSU__USB1_COHERENCY {0} \ # CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__USB1__RESET__ENABLE {0} \ # CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ # CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ # CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ # CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ # CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ # CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ # CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ # CONFIG.PSU__USB__RESET__MODE {Boot Pin} \ # CONFIG.PSU__USB__RESET__POLARITY {Active Low} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ # CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ # CONFIG.PSU__USE__ADMA {0} \ # CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ # CONFIG.PSU__USE__AUDIO {0} \ # CONFIG.PSU__USE__CLK {0} \ # CONFIG.PSU__USE__CLK0 {0} \ # CONFIG.PSU__USE__CLK1 {0} \ # CONFIG.PSU__USE__CLK2 {0} \ # CONFIG.PSU__USE__CLK3 {0} \ # CONFIG.PSU__USE__CROSS_TRIGGER {0} \ # CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ # CONFIG.PSU__USE__DEBUG__TEST {0} \ # CONFIG.PSU__USE__EVENT_RPU {0} \ # CONFIG.PSU__USE__FABRIC__RST {1} \ # CONFIG.PSU__USE__FTM {0} \ # CONFIG.PSU__USE__GDMA {0} \ # CONFIG.PSU__USE__IRQ {0} \ # CONFIG.PSU__USE__IRQ0 {1} \ # CONFIG.PSU__USE__IRQ1 {1} \ # CONFIG.PSU__USE__M_AXI_GP0 {0} \ # CONFIG.PSU__USE__M_AXI_GP1 {0} \ # CONFIG.PSU__USE__M_AXI_GP2 {1} \ # CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ # CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ # CONFIG.PSU__USE__RST0 {0} \ # CONFIG.PSU__USE__RST1 {0} \ # CONFIG.PSU__USE__RST2 {0} \ # CONFIG.PSU__USE__RST3 {0} \ # CONFIG.PSU__USE__RTC {0} \ # CONFIG.PSU__USE__STM {0} \ # CONFIG.PSU__USE__S_AXI_ACE {0} \ # CONFIG.PSU__USE__S_AXI_ACP {0} \ # CONFIG.PSU__USE__S_AXI_GP0 {0} \ # CONFIG.PSU__USE__S_AXI_GP1 {0} \ # CONFIG.PSU__USE__S_AXI_GP2 {1} \ # CONFIG.PSU__USE__S_AXI_GP3 {0} \ # CONFIG.PSU__USE__S_AXI_GP4 {1} \ # CONFIG.PSU__USE__S_AXI_GP5 {0} \ # CONFIG.PSU__USE__S_AXI_GP6 {1} \ # CONFIG.PSU__USE__USB3_0_HUB {0} \ # CONFIG.PSU__USE__USB3_1_HUB {0} \ # CONFIG.PSU__USE__VIDEO {0} \ # CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ # CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ # CONFIG.QSPI_BOARD_INTERFACE {custom} \ # CONFIG.SATA_BOARD_INTERFACE {custom} \ # CONFIG.SD0_BOARD_INTERFACE {custom} \ # CONFIG.SD1_BOARD_INTERFACE {custom} \ # CONFIG.SPI0_BOARD_INTERFACE {custom} \ # CONFIG.SPI1_BOARD_INTERFACE {custom} \ # CONFIG.SUBPRESET1 {Custom} \ # CONFIG.SUBPRESET2 {Custom} \ # CONFIG.SWDT0_BOARD_INTERFACE {custom} \ # CONFIG.SWDT1_BOARD_INTERFACE {custom} \ # CONFIG.TRACE_BOARD_INTERFACE {custom} \ # CONFIG.TTC0_BOARD_INTERFACE {custom} \ # CONFIG.TTC1_BOARD_INTERFACE {custom} \ # CONFIG.TTC2_BOARD_INTERFACE {custom} \ # CONFIG.TTC3_BOARD_INTERFACE {custom} \ # CONFIG.UART0_BOARD_INTERFACE {custom} \ # CONFIG.UART1_BOARD_INTERFACE {custom} \ # CONFIG.USB0_BOARD_INTERFACE {custom} \ # CONFIG.USB1_BOARD_INTERFACE {custom} \ # ] $ps_e_0 # # # Create instance: reset_control, and set properties # set reset_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reset_control ] # set_property -dict [ list \ # CONFIG.C_ALL_OUTPUTS {1} \ # ] $reset_control # # # Create instance: shutdown_HP0_FPD, and set properties # set shutdown_HP0_FPD [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_axi_shutdown_manager:1.0 shutdown_HP0_FPD ] # set_property -dict [ list \ # CONFIG.CTRL_INTERFACE_TYPE {1} \ # CONFIG.DP_AXI_DATA_WIDTH {128} \ # ] $shutdown_HP0_FPD # # # Create instance: shutdown_HP2_FPD, and set properties # set shutdown_HP2_FPD [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_axi_shutdown_manager:1.0 shutdown_HP2_FPD ] # set_property -dict [ list \ # CONFIG.CTRL_INTERFACE_TYPE {1} \ # CONFIG.DP_AXI_DATA_WIDTH {128} \ # ] $shutdown_HP2_FPD # # # Create instance: shutdown_LPD, and set properties # set shutdown_LPD [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_axi_shutdown_manager:1.0 shutdown_LPD ] # set_property -dict [ list \ # CONFIG.CTRL_INTERFACE_TYPE {1} \ # CONFIG.DP_AXI_DATA_WIDTH {128} \ # ] $shutdown_LPD # # # Create instance: vcc_const, and set properties # set vcc_const [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 vcc_const ] # set_property -dict [ list \ # CONFIG.CONST_VAL {1} \ # ] $vcc_const # # # Create instance: video # create_hier_cell_video [current_bd_instance .] video # # # Create instance: xlconcat0, and set properties # set xlconcat0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat0 ] # set_property -dict [ list \ # CONFIG.NUM_PORTS {9} \ # ] $xlconcat0 # # # Create instance: xlconcat_0, and set properties # set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] # set_property -dict [ list \ # CONFIG.NUM_PORTS {8} \ # ] $xlconcat_0 # # # Create instance: xlconcat_1, and set properties # set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] # set_property -dict [ list \ # CONFIG.NUM_PORTS {8} \ # ] $xlconcat_1 # # # Create instance: xlslice_0, and set properties # set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] # # # Create instance: xlslice_1, and set properties # set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] # set_property -dict [ list \ # CONFIG.DIN_FROM {1} \ # CONFIG.DIN_TO {1} \ # CONFIG.DOUT_WIDTH {1} \ # ] $xlslice_1 # # # Create interface connections # connect_bd_intf_net -intf_net address_remap_0_M_AXI_out [get_bd_intf_pins address_remap_0/M_AXI_out] [get_bd_intf_pins shutdown_LPD/S_AXI] # connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports dip_switch_4bits] [get_bd_intf_pins gpio_sws/GPIO] # connect_bd_intf_net -intf_net axi_gpio_0_GPIO1 [get_bd_intf_ports led_4bits] [get_bd_intf_pins gpio_leds/GPIO] # connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports push_button_4bits] [get_bd_intf_pins gpio_btns/GPIO] # connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins address_remap_0/S_AXI_in] [get_bd_intf_pins axi_interconnect_0/M00_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M05_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins axi_interconnect/M05_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M06_AXI [get_bd_intf_pins axi_interconnect/M06_AXI] [get_bd_intf_pins reset_control/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M07_AXI [get_bd_intf_pins axi_interconnect/M07_AXI] [get_bd_intf_pins video/s_axi_AXILiteS] # connect_bd_intf_net -intf_net axi_interconnect_M08_AXI [get_bd_intf_pins axi_interconnect/M08_AXI] [get_bd_intf_pins video/s_axi_AXILiteS1] # connect_bd_intf_net -intf_net axi_interconnect_M09_AXI [get_bd_intf_pins axi_interconnect/M09_AXI] [get_bd_intf_pins video/s_axi_AXILiteS2] # connect_bd_intf_net -intf_net axi_interconnect_M10_AXI [get_bd_intf_pins axi_interconnect/M10_AXI] [get_bd_intf_pins video/s_axi_AXILiteS3] # connect_bd_intf_net -intf_net axi_interconnect_M11_AXI [get_bd_intf_pins axi_interconnect/M11_AXI] [get_bd_intf_pins iop_pmod0/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M12_AXI [get_bd_intf_pins axi_interconnect/M12_AXI] [get_bd_intf_pins iop_pmod1/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M13_AXI [get_bd_intf_pins axi_interconnect/M13_AXI] [get_bd_intf_pins gpio_sws/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M14_AXI [get_bd_intf_pins axi_interconnect/M14_AXI] [get_bd_intf_pins gpio_btns/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M15_AXI [get_bd_intf_pins axi_interconnect/M15_AXI] [get_bd_intf_pins gpio_leds/S_AXI] # connect_bd_intf_net -intf_net axi_interconnect_M16_AXI [get_bd_intf_pins axi_interconnect/M16_AXI] [get_bd_intf_pins shutdown_HP0_FPD/S_AXI_CTRL] # connect_bd_intf_net -intf_net axi_interconnect_M17_AXI [get_bd_intf_pins axi_interconnect/M17_AXI] [get_bd_intf_pins shutdown_LPD/S_AXI_CTRL] # connect_bd_intf_net -intf_net axi_interconnect_M18_AXI [get_bd_intf_pins axi_interconnect/M18_AXI] [get_bd_intf_pins shutdown_HP2_FPD/S_AXI_CTRL] # connect_bd_intf_net -intf_net axi_mem_intercon_1_M00_AXI [get_bd_intf_pins axi_mem_intercon_1/M00_AXI] [get_bd_intf_pins shutdown_HP2_FPD/S_AXI] # connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins shutdown_HP0_FPD/S_AXI] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins video/M_AXI_MM2S] # connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins axi_mem_intercon_1/S00_AXI] [get_bd_intf_pins video/M_AXI_S2MM] # connect_bd_intf_net -intf_net intf_net_axi_interconnect_M04_AXI [get_bd_intf_pins axi_interconnect/M04_AXI] [get_bd_intf_pins fmch_axi_iic/S_AXI] # connect_bd_intf_net -intf_net intf_net_bdry_in_DRU_CLK_IN [get_bd_intf_ports DRU_CLK_IN] [get_bd_intf_pins video/DRU_CLK_IN] # connect_bd_intf_net -intf_net intf_net_v_hdmi_rx_ss_DDC_OUT [get_bd_intf_ports RX_DDC_OUT] [get_bd_intf_pins video/RX_DDC_OUT] # connect_bd_intf_net -intf_net intf_net_v_hdmi_tx_ss_DDC_OUT [get_bd_intf_ports TX_DDC_OUT] [get_bd_intf_pins video/TX_DDC_OUT] # connect_bd_intf_net -intf_net intf_net_zynq_us_M_AXI_HPM0_LPD [get_bd_intf_pins axi_interconnect/S00_AXI] [get_bd_intf_pins ps_e_0/M_AXI_HPM0_LPD] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_IIC [get_bd_intf_ports fmch_iic] [get_bd_intf_pins fmch_axi_iic/IIC] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M00_AXI [get_bd_intf_pins axi_interconnect/M00_AXI] [get_bd_intf_pins video/vid_phy_axi4lite] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M01_AXI [get_bd_intf_pins axi_interconnect/M01_AXI] [get_bd_intf_pins video/S_AXI_CPU_IN] # connect_bd_intf_net -intf_net intf_net_zynq_us_ss_0_M02_AXI [get_bd_intf_pins axi_interconnect/M02_AXI] [get_bd_intf_pins video/S_AXI_CPU_IN1] # connect_bd_intf_net -intf_net mdm_0_MBDEBUG_0 [get_bd_intf_pins iop_pmod0/DEBUG] [get_bd_intf_pins mdm/MBDEBUG_0] # connect_bd_intf_net -intf_net mdm_0_MBDEBUG_1 [get_bd_intf_pins iop_pmod1/DEBUG] [get_bd_intf_pins mdm/MBDEBUG_1] # connect_bd_intf_net -intf_net pmod0_M_AXI [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins iop_pmod0/M_AXI] # connect_bd_intf_net -intf_net pmod1_M_AXI [get_bd_intf_pins axi_interconnect_0/S01_AXI] [get_bd_intf_pins iop_pmod1/M_AXI] # connect_bd_intf_net -intf_net pr_axi_shutdown_mana_0_M_AXI [get_bd_intf_pins ps_e_0/S_AXI_LPD] [get_bd_intf_pins shutdown_LPD/M_AXI] # connect_bd_intf_net -intf_net shutdown_HP0_M_AXI [get_bd_intf_pins ps_e_0/S_AXI_HP0_FPD] [get_bd_intf_pins shutdown_HP0_FPD/M_AXI] # connect_bd_intf_net -intf_net shutdown_HP2_M_AXI [get_bd_intf_pins ps_e_0/S_AXI_HP2_FPD] [get_bd_intf_pins shutdown_HP2_FPD/M_AXI] # connect_bd_intf_net -intf_net zynq_us_ss_0_M03_AXI [get_bd_intf_pins axi_interconnect/M03_AXI] [get_bd_intf_pins video/S_AXI_LITE] # # # Create port connections # connect_bd_net -net ARESETN_1 [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn] # connect_bd_net -net Net [get_bd_ports pmod0] [get_bd_pins pmod0_buf/IOBUF_IO_IO] # connect_bd_net -net Net1 [get_bd_ports pmod1] [get_bd_pins pmod1_buf/IOBUF_IO_IO] # connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins reset_control/gpio_io_o] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] # connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins xlconcat_0/In0] # connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins video/mm2s_introut] [get_bd_pins xlconcat0/In4] # connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins video/s2mm_introut] [get_bd_pins xlconcat0/In3] # connect_bd_net -net data_i_1 [get_bd_pins iop_pmod0/data_i] [get_bd_pins pmod0_buf/IOBUF_IO_O] # connect_bd_net -net data_i_2 [get_bd_pins iop_pmod1/data_i] [get_bd_pins pmod1_buf/IOBUF_IO_O] # connect_bd_net -net gpio_btns_ip2intc_irpt [get_bd_pins gpio_btns/ip2intc_irpt] [get_bd_pins xlconcat0/In8] # connect_bd_net -net gpio_sws_ip2intc_irpt [get_bd_pins gpio_sws/ip2intc_irpt] [get_bd_pins xlconcat0/In7] # connect_bd_net -net mb_pmod1_intr_ack_Dout [get_bd_pins iop_pmod1/intr_ack] [get_bd_pins mb_iop_pmod1_intr_ack/Dout] # connect_bd_net -net mb_pmod1_reset_Dout [get_bd_pins iop_pmod1/aux_reset_in] [get_bd_pins mb_iop_pmod1_reset/Dout] # connect_bd_net -net mdm_0_Debug_SYS_Rst [get_bd_pins iop_pmod0/mb_debug_sys_rst] [get_bd_pins iop_pmod1/mb_debug_sys_rst] [get_bd_pins mdm/Debug_SYS_Rst] # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_N_IN [get_bd_ports HDMI_RX_CLK_N_IN] [get_bd_pins video/HDMI_RX_CLK_N_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_CLK_P_IN [get_bd_ports HDMI_RX_CLK_P_IN] [get_bd_pins video/HDMI_RX_CLK_P_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_N_IN [get_bd_ports HDMI_RX_DAT_N_IN] [get_bd_pins video/HDMI_RX_DAT_N_IN] # connect_bd_net -net net_bdry_in_HDMI_RX_DAT_P_IN [get_bd_ports HDMI_RX_DAT_P_IN] [get_bd_pins video/HDMI_RX_DAT_P_IN] # connect_bd_net -net net_bdry_in_IDT_8T49N241_LOL_IN [get_bd_ports IDT_8T49N241_LOL_IN] [get_bd_pins video/IDT_8T49N241_LOL_IN] # connect_bd_net -net net_bdry_in_RX_DET_IN [get_bd_ports RX_DET_IN] [get_bd_pins video/RX_DET_IN] # connect_bd_net -net net_bdry_in_TX_HPD_IN [get_bd_ports TX_HPD_IN] [get_bd_pins video/TX_HPD_IN] # connect_bd_net -net net_bdry_in_TX_REFCLK_N_IN [get_bd_ports TX_REFCLK_N_IN] [get_bd_pins video/TX_REFCLK_N_IN] # connect_bd_net -net net_bdry_in_TX_REFCLK_P_IN [get_bd_ports TX_REFCLK_P_IN] [get_bd_pins video/TX_REFCLK_P_IN] # connect_bd_net -net net_bdry_in_reset [get_bd_ports reset] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] # connect_bd_net -net net_rst_processor_1_100M_interconnect_aresetn [get_bd_pins axi_interconnect/ARESETN] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] # connect_bd_net -net net_v_hdmi_rx_ss_hpd [get_bd_ports RX_HPD_OUT] [get_bd_pins video/RX_HPD_OUT] # connect_bd_net -net net_v_hdmi_rx_ss_irq [get_bd_pins video/irq] [get_bd_pins xlconcat0/In1] # connect_bd_net -net net_v_hdmi_tx_ss_irq [get_bd_pins video/irq1] [get_bd_pins xlconcat0/In2] # connect_bd_net -net net_vcc_const_dout [get_bd_ports TX_EN_OUT] [get_bd_pins vcc_const/dout] [get_bd_pins video/TX_EN_OUT] # connect_bd_net -net net_vid_phy_controller_irq [get_bd_pins video/irq2] [get_bd_pins xlconcat0/In0] # connect_bd_net -net net_vid_phy_controller_phy_txn_out [get_bd_ports HDMI_TX_DAT_N_OUT] [get_bd_pins video/HDMI_TX_DAT_N_OUT] # connect_bd_net -net net_vid_phy_controller_phy_txp_out [get_bd_ports HDMI_TX_DAT_P_OUT] [get_bd_pins video/HDMI_TX_DAT_P_OUT] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_n [get_bd_ports RX_REFCLK_N_OUT] [get_bd_pins video/RX_REFCLK_N_OUT] # connect_bd_net -net net_vid_phy_controller_rx_tmds_clk_p [get_bd_ports RX_REFCLK_P_OUT] [get_bd_pins video/RX_REFCLK_P_OUT] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_n [get_bd_ports HDMI_TX_CLK_N_OUT] [get_bd_pins video/HDMI_TX_CLK_N_OUT] # connect_bd_net -net net_vid_phy_controller_tx_tmds_clk_p [get_bd_ports HDMI_TX_CLK_P_OUT] [get_bd_pins video/HDMI_TX_CLK_P_OUT] # connect_bd_net -net net_zynq_us_pl_resetn0 [get_bd_pins proc_sys_reset_0/aux_reset_in] [get_bd_pins proc_sys_reset_0/dcm_locked] [get_bd_pins proc_sys_reset_1/aux_reset_in] [get_bd_pins proc_sys_reset_1/dcm_locked] [get_bd_pins proc_sys_reset_2/aux_reset_in] [get_bd_pins proc_sys_reset_2/dcm_locked] [get_bd_pins proc_sys_reset_3/aux_reset_in] [get_bd_pins proc_sys_reset_3/dcm_locked] [get_bd_pins ps_e_0/pl_resetn0] # connect_bd_net -net net_zynq_us_ss_0_clk_out2 [get_bd_pins axi_interconnect/M07_ACLK] [get_bd_pins axi_interconnect/M08_ACLK] [get_bd_pins axi_interconnect/M09_ACLK] [get_bd_pins axi_interconnect/M10_ACLK] [get_bd_pins axi_interconnect/M16_ACLK] [get_bd_pins axi_interconnect/M18_ACLK] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon_1/ACLK] [get_bd_pins axi_mem_intercon_1/M00_ACLK] [get_bd_pins axi_mem_intercon_1/S00_ACLK] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins ps_e_0/pl_clk1] [get_bd_pins ps_e_0/saxihp0_fpd_aclk] [get_bd_pins ps_e_0/saxihp2_fpd_aclk] [get_bd_pins shutdown_HP0_FPD/clk] [get_bd_pins shutdown_HP2_FPD/clk] [get_bd_pins video/aclk] # connect_bd_net -net net_zynq_us_ss_0_dcm_locked [get_bd_pins axi_interconnect/M07_ARESETN] [get_bd_pins axi_interconnect/M08_ARESETN] [get_bd_pins axi_interconnect/M09_ARESETN] [get_bd_pins axi_interconnect/M10_ARESETN] [get_bd_pins axi_interconnect/M16_ARESETN] [get_bd_pins axi_interconnect/M18_ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon_1/M00_ARESETN] [get_bd_pins axi_mem_intercon_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] [get_bd_pins shutdown_HP0_FPD/resetn] [get_bd_pins shutdown_HP2_FPD/resetn] [get_bd_pins video/aresetn] # connect_bd_net -net net_zynq_us_ss_0_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_interconnect/M00_ARESETN] [get_bd_pins axi_interconnect/M01_ARESETN] [get_bd_pins axi_interconnect/M02_ARESETN] [get_bd_pins axi_interconnect/M03_ARESETN] [get_bd_pins axi_interconnect/M04_ARESETN] [get_bd_pins axi_interconnect/M05_ARESETN] [get_bd_pins axi_interconnect/M06_ARESETN] [get_bd_pins axi_interconnect/M11_ARESETN] [get_bd_pins axi_interconnect/M12_ARESETN] [get_bd_pins axi_interconnect/M13_ARESETN] [get_bd_pins axi_interconnect/M14_ARESETN] [get_bd_pins axi_interconnect/M15_ARESETN] [get_bd_pins axi_interconnect/M17_ARESETN] [get_bd_pins axi_interconnect/S00_ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins fmch_axi_iic/s_axi_aresetn] [get_bd_pins gpio_btns/s_axi_aresetn] [get_bd_pins gpio_leds/s_axi_aresetn] [get_bd_pins gpio_sws/s_axi_aresetn] [get_bd_pins iop_pmod0/s_axi_aresetn] [get_bd_pins iop_pmod1/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins reset_control/s_axi_aresetn] [get_bd_pins video/s_axi_cpu_aresetn] # connect_bd_net -net net_zynq_us_ss_0_s_axi_aclk [get_bd_pins address_remap_0/m_axi_out_aclk] [get_bd_pins address_remap_0/s_axi_in_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_interconnect/ACLK] [get_bd_pins axi_interconnect/M00_ACLK] [get_bd_pins axi_interconnect/M01_ACLK] [get_bd_pins axi_interconnect/M02_ACLK] [get_bd_pins axi_interconnect/M03_ACLK] [get_bd_pins axi_interconnect/M04_ACLK] [get_bd_pins axi_interconnect/M05_ACLK] [get_bd_pins axi_interconnect/M06_ACLK] [get_bd_pins axi_interconnect/M11_ACLK] [get_bd_pins axi_interconnect/M12_ACLK] [get_bd_pins axi_interconnect/M13_ACLK] [get_bd_pins axi_interconnect/M14_ACLK] [get_bd_pins axi_interconnect/M15_ACLK] [get_bd_pins axi_interconnect/M17_ACLK] [get_bd_pins axi_interconnect/S00_ACLK] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins fmch_axi_iic/s_axi_aclk] [get_bd_pins gpio_btns/s_axi_aclk] [get_bd_pins gpio_leds/s_axi_aclk] [get_bd_pins gpio_sws/s_axi_aclk] [get_bd_pins iop_pmod0/clk_100M] [get_bd_pins iop_pmod1/clk_100M] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins ps_e_0/pl_clk0] [get_bd_pins ps_e_0/saxi_lpd_aclk] [get_bd_pins reset_control/s_axi_aclk] [get_bd_pins shutdown_LPD/clk] [get_bd_pins video/s_axi_cpu_aclk] # connect_bd_net -net pmod0_data_o [get_bd_pins iop_pmod0/data_o] [get_bd_pins pmod0_buf/IOBUF_IO_I] # connect_bd_net -net pmod0_intr_req [get_bd_pins iop_pmod0/intr_req] [get_bd_pins xlconcat0/In5] # connect_bd_net -net pmod0_intr_req_Dout [get_bd_pins iop_pmod0/intr_ack] [get_bd_pins mb_iop_pmod0_intr_ack/Dout] # connect_bd_net -net pmod0_peripheral_aresetn [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins iop_pmod0/peripheral_aresetn] # connect_bd_net -net pmod0_reset_Dout [get_bd_pins iop_pmod0/aux_reset_in] [get_bd_pins mb_iop_pmod0_reset/Dout] # connect_bd_net -net pmod0_tri_o [get_bd_pins iop_pmod0/tri_o] [get_bd_pins pmod0_buf/IOBUF_IO_T] # connect_bd_net -net pmod1_data_o [get_bd_pins iop_pmod1/data_o] [get_bd_pins pmod1_buf/IOBUF_IO_I] # connect_bd_net -net pmod1_intr_req [get_bd_pins iop_pmod1/intr_req] [get_bd_pins xlconcat0/In6] # connect_bd_net -net pmod1_peripheral_aresetn [get_bd_pins address_remap_0/m_axi_out_aresetn] [get_bd_pins address_remap_0/s_axi_in_aresetn] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins iop_pmod1/peripheral_aresetn] [get_bd_pins shutdown_LPD/resetn] # connect_bd_net -net pmod1_tri_o [get_bd_pins iop_pmod1/tri_o] [get_bd_pins pmod1_buf/IOBUF_IO_T] # connect_bd_net -net xlconcat0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat0/dout] # connect_bd_net -net xlconcat_0_dout [get_bd_pins ps_e_0/pl_ps_irq0] [get_bd_pins xlconcat_0/dout] # connect_bd_net -net xlconcat_1_dout [get_bd_pins ps_e_0/pl_ps_irq1] [get_bd_pins xlconcat_1/dout] # connect_bd_net -net xlslice_0_Dout [get_bd_ports IDT_8T49N241_RST_OUT] [get_bd_pins xlslice_0/Dout] # connect_bd_net -net xlslice_1_Dout [get_bd_ports HDMI_RX_LS_OE] [get_bd_pins xlslice_1/Dout] # connect_bd_net -net zynq_us_emio_gpio_o [get_bd_pins mb_iop_pmod0_intr_ack/Din] [get_bd_pins mb_iop_pmod0_reset/Din] [get_bd_pins mb_iop_pmod1_intr_ack/Din] [get_bd_pins mb_iop_pmod1_reset/Din] [get_bd_pins ps_e_0/emio_gpio_o] # connect_bd_net -net zynq_us_pl_clk2 [get_bd_pins proc_sys_reset_2/slowest_sync_clk] [get_bd_pins ps_e_0/pl_clk2] # connect_bd_net -net zynq_us_pl_clk3 [get_bd_pins proc_sys_reset_3/slowest_sync_clk] [get_bd_pins ps_e_0/pl_clk3] # # # Create address segments # assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces address_remap_0/M_AXI_out] [get_bd_addr_segs ps_e_0/SAXIGP6/LPD_DDR_LOW] -force # assign_bd_address -offset 0x80044000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs reset_control/S_AXI/Reg] -force # assign_bd_address -offset 0x80045000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs gpio_btns/S_AXI/Reg] -force # assign_bd_address -offset 0x80043000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force # assign_bd_address -offset 0x80042000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/axi_vdma/S_AXI_LITE/Reg] -force # assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_out/color_convert/s_axi_AXILiteS/Reg] -force # assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_in/color_convert/s_axi_AXILiteS/Reg] -force # assign_bd_address -offset 0x80041000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs fmch_axi_iic/S_AXI/Reg] -force # assign_bd_address -offset 0x80046000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs gpio_leds/S_AXI/Reg] -force # assign_bd_address -offset 0x80040000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs gpio_sws/S_AXI/Reg] -force # assign_bd_address -offset 0x800A0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs iop_pmod0/mb_bram_ctrl/S_AXI/Mem0] -force # assign_bd_address -offset 0x800B0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs iop_pmod1/mb_bram_ctrl/S_AXI/Mem0] -force # assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_in/pixel_pack/s_axi_AXILiteS/Reg] -force # assign_bd_address -offset 0x80080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_out/pixel_unpack/s_axi_AXILiteS/Reg] -force # assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs shutdown_HP0_FPD/S_AXI_CTRL/Reg] -force # assign_bd_address -offset 0x80090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs shutdown_HP2_FPD/S_AXI_CTRL/Reg] -force # assign_bd_address -offset 0x800C0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs shutdown_LPD/S_AXI_CTRL/Reg] -force # assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_in/frontend/S_AXI_CPU_IN/Reg] -force # assign_bd_address -offset 0x80020000 -range 0x00020000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/hdmi_out/frontend/S_AXI_CPU_IN/Reg] -force # assign_bd_address -offset 0x800D0000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs video/phy/vid_phy_controller/vid_phy_axi4lite/Reg] -force # assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs address_remap_0/S_AXI_in/memory] -force # assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/gpio/S_AXI/Reg] -force # assign_bd_address -offset 0x40800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/iic/S_AXI/Reg] -force # assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/intc/S_AXI/Reg] -force # assign_bd_address -offset 0x40010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/intr/S_AXI/Reg] -force # assign_bd_address -offset 0x44A20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/io_switch/S_AXI/S_AXI_reg] -force # assign_bd_address -offset 0x00000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/lmb/lmb_bram_if_cntlr/SLMB1/Mem] -force # assign_bd_address -offset 0x00000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Instruction] [get_bd_addr_segs iop_pmod0/lmb/lmb_bram_if_cntlr/SLMB/Mem] -force # assign_bd_address -offset 0x44A10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/spi/AXI_LITE/Reg] -force # assign_bd_address -offset 0x41C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod0/mb/Data] [get_bd_addr_segs iop_pmod0/timer/S_AXI/Reg] -force # assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs address_remap_0/S_AXI_in/memory] -force # assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/gpio/S_AXI/Reg] -force # assign_bd_address -offset 0x40800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/iic/S_AXI/Reg] -force # assign_bd_address -offset 0x44A10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/spi/AXI_LITE/Reg] -force # assign_bd_address -offset 0x00000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Instruction] [get_bd_addr_segs iop_pmod1/lmb/lmb_bram_if_cntlr/SLMB/Mem] -force # assign_bd_address -offset 0x44A20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/io_switch/S_AXI/S_AXI_reg] -force # assign_bd_address -offset 0x00000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/lmb/lmb_bram_if_cntlr/SLMB1/Mem] -force # assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/intc/S_AXI/Reg] -force # assign_bd_address -offset 0x41C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/timer/S_AXI/Reg] -force # assign_bd_address -offset 0x40010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces iop_pmod1/mb/Data] [get_bd_addr_segs iop_pmod1/intr/S_AXI/Reg] -force # assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_S2MM] [get_bd_addr_segs ps_e_0/SAXIGP4/HP2_DDR_LOW] -force # assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_MM2S] [get_bd_addr_segs ps_e_0/SAXIGP2/HP0_DDR_LOW] -force # assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_MM2S] [get_bd_addr_segs ps_e_0/SAXIGP2/HP0_LPS_OCM] -force # assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_MM2S] [get_bd_addr_segs ps_e_0/SAXIGP2/HP0_QSPI] -force # assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_S2MM] [get_bd_addr_segs ps_e_0/SAXIGP4/HP2_LPS_OCM] -force # assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces video/axi_vdma/Data_S2MM] [get_bd_addr_segs ps_e_0/SAXIGP4/HP2_QSPI] -force # # # # Restore current instance # current_bd_instance $oldCurInst # # # Create PFM attributes # set_property PFM_NAME {xilinx.com:xd:${overlay_name}:1.0} [get_files [current_bd_design].bd] # set_property PFM.CLOCK { \ # pl_clk0 {id "0" is_default "true" \ # proc_sys_reset "proc_sys_reset_0" status "fixed"} \ # pl_clk1 {id "1" is_default "false" \ # proc_sys_reset "proc_sys_reset_1" status "fixed"} \ # pl_clk2 {id "2" is_default "false" \ # proc_sys_reset "proc_sys_reset_2" status "fixed"} \ # pl_clk3 {id "3" is_default "false" \ # proc_sys_reset "proc_sys_reset_3" status "fixed"} \ # } [get_bd_cells /ps_e_0] # set_property PFM.AXI_PORT { \ # M_AXI_HPM0_FPD {memport "M_AXI_GP"} \ # M_AXI_HPM1_FPD {memport "M_AXI_GP"} \ # S_AXI_HPC0_FPD {memport "S_AXI_HPC"} \ # S_AXI_HPC1_FPD {memport "S_AXI_HPC"} \ # S_AXI_HP1_FPD {memport "S_AXI_HP"} \ # S_AXI_HP3_FPD {memport "S_AXI_HP"} \ # S_AXI_LPD {memport "S_AXI_HP"} \ # } [get_bd_cells /ps_e_0] # set intVar0 [] # for {set i 1} {$i < 8} {incr i} { # lappend intVar0 In$i {} # } # set_property PFM.IRQ $intVar0 [get_bd_cells /xlconcat_0] # set intVar1 [] # for {set i 0} {$i < 8} {incr i} { # lappend intVar1 In$i {} # } # set_property PFM.IRQ $intVar1 [get_bd_cells /xlconcat_1] # # validate_bd_design # save_bd_design # } # create_root_design "" INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide. INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide. WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_tri_o is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod0/clk_100M(clk) and /iop_pmod0/dff_en_reset_vector_0/clk(undef) INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_1: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide. INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_1: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide. WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_tri_o is being overridden by the user. This pin will not be connected as a part of interface connection io WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod1/clk_100M(clk) and /iop_pmod1/dff_en_reset_vector_0/clk(undef) INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose. INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e create_bd_cell: Time (s): cpu = 00:00:28 ; elapsed = 00:01:01 . Memory (MB): peak = 8386.867 ; gain = 1019.656 ; free physical = 9929 ; free virtual = 16531 WARNING: [BD 41-1306] The connection to interface pin /reset_control/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_0/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_1/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_2/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_3/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) WARNING: [BD 41-1306] The connection to interface pin /ps_e_0/emio_gpio_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 Slave segment '/ps_e_0/SAXIGP6/LPD_DDR_LOW' is being assigned into address space '/address_remap_0/M_AXI_out' at <0x0000_0000 [ 2G ]>. Slave segment '/reset_control/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_4000 [ 4K ]>. Slave segment '/gpio_btns/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_5000 [ 4K ]>. Slave segment '/axi_intc_0/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_3000 [ 4K ]>. Slave segment '/video/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_2000 [ 4K ]>. Slave segment '/video/hdmi_out/color_convert/s_axi_AXILiteS/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8001_0000 [ 64K ]>. Slave segment '/video/hdmi_in/color_convert/s_axi_AXILiteS/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8005_0000 [ 64K ]>. Slave segment '/fmch_axi_iic/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_1000 [ 4K ]>. Slave segment '/gpio_leds/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_6000 [ 4K ]>. Slave segment '/gpio_sws/S_AXI/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8004_0000 [ 4K ]>. Slave segment '/iop_pmod0/mb_bram_ctrl/S_AXI/Mem0' is being assigned into address space '/ps_e_0/Data' at <0x800A_0000 [ 64K ]>. Slave segment '/iop_pmod1/mb_bram_ctrl/S_AXI/Mem0' is being assigned into address space '/ps_e_0/Data' at <0x800B_0000 [ 64K ]>. Slave segment '/video/hdmi_in/pixel_pack/s_axi_AXILiteS/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8007_0000 [ 64K ]>. Slave segment '/video/hdmi_out/pixel_unpack/s_axi_AXILiteS/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8008_0000 [ 64K ]>. Slave segment '/shutdown_HP0_FPD/S_AXI_CTRL/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8006_0000 [ 64K ]>. Slave segment '/shutdown_HP2_FPD/S_AXI_CTRL/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8009_0000 [ 64K ]>. Slave segment '/shutdown_LPD/S_AXI_CTRL/Reg' is being assigned into address space '/ps_e_0/Data' at <0x800C_0000 [ 64K ]>. Slave segment '/video/hdmi_in/frontend/S_AXI_CPU_IN/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8000_0000 [ 64K ]>. Slave segment '/video/hdmi_out/frontend/S_AXI_CPU_IN/Reg' is being assigned into address space '/ps_e_0/Data' at <0x8002_0000 [ 128K ]>. Slave segment '/video/phy/vid_phy_controller/vid_phy_axi4lite/Reg' is being assigned into address space '/ps_e_0/Data' at <0x800D_0000 [ 64K ]>. Slave segment '/address_remap_0/S_AXI_in/memory' is being assigned into address space '/iop_pmod0/mb/Data' at <0x8000_0000 [ 2G ]>. Slave segment '/iop_pmod0/gpio/S_AXI/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x4000_0000 [ 64K ]>. Slave segment '/iop_pmod0/iic/S_AXI/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x4080_0000 [ 64K ]>. Slave segment '/iop_pmod0/intc/S_AXI/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x4120_0000 [ 64K ]>. Slave segment '/iop_pmod0/intr/S_AXI/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x4001_0000 [ 64K ]>. Slave segment '/iop_pmod0/io_switch/S_AXI/S_AXI_reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x44A2_0000 [ 64K ]>. Slave segment '/iop_pmod0/lmb/lmb_bram_if_cntlr/SLMB1/Mem' is being assigned into address space '/iop_pmod0/mb/Data' at <0x0000_0000 [ 64K ]>. Slave segment '/iop_pmod0/lmb/lmb_bram_if_cntlr/SLMB/Mem' is being assigned into address space '/iop_pmod0/mb/Instruction' at <0x0000_0000 [ 64K ]>. Slave segment '/iop_pmod0/spi/AXI_LITE/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x44A1_0000 [ 64K ]>. Slave segment '/iop_pmod0/timer/S_AXI/Reg' is being assigned into address space '/iop_pmod0/mb/Data' at <0x41C0_0000 [ 64K ]>. Slave segment '/address_remap_0/S_AXI_in/memory' is being assigned into address space '/iop_pmod1/mb/Data' at <0x8000_0000 [ 2G ]>. Slave segment '/iop_pmod1/gpio/S_AXI/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x4000_0000 [ 64K ]>. Slave segment '/iop_pmod1/iic/S_AXI/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x4080_0000 [ 64K ]>. Slave segment '/iop_pmod1/spi/AXI_LITE/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x44A1_0000 [ 64K ]>. Slave segment '/iop_pmod1/lmb/lmb_bram_if_cntlr/SLMB/Mem' is being assigned into address space '/iop_pmod1/mb/Instruction' at <0x0000_0000 [ 64K ]>. Slave segment '/iop_pmod1/io_switch/S_AXI/S_AXI_reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x44A2_0000 [ 64K ]>. Slave segment '/iop_pmod1/lmb/lmb_bram_if_cntlr/SLMB1/Mem' is being assigned into address space '/iop_pmod1/mb/Data' at <0x0000_0000 [ 64K ]>. Slave segment '/iop_pmod1/intc/S_AXI/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x4120_0000 [ 64K ]>. Slave segment '/iop_pmod1/timer/S_AXI/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x41C0_0000 [ 64K ]>. Slave segment '/iop_pmod1/intr/S_AXI/Reg' is being assigned into address space '/iop_pmod1/mb/Data' at <0x4001_0000 [ 64K ]>. Slave segment '/ps_e_0/SAXIGP4/HP2_DDR_LOW' is being assigned into address space '/video/axi_vdma/Data_S2MM' at <0x0000_0000 [ 2G ]>. Slave segment '/ps_e_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/video/axi_vdma/Data_MM2S' at <0x0000_0000 [ 2G ]>. Slave segment '/ps_e_0/SAXIGP2/HP0_LPS_OCM' is being assigned into address space '/video/axi_vdma/Data_MM2S' at <0xFF00_0000 [ 16M ]>. Slave segment '/ps_e_0/SAXIGP2/HP0_QSPI' is being assigned into address space '/video/axi_vdma/Data_MM2S' at <0xC000_0000 [ 512M ]>. Slave segment '/ps_e_0/SAXIGP4/HP2_LPS_OCM' is being assigned into address space '/video/axi_vdma/Data_S2MM' at <0xFF00_0000 [ 16M ]>. Slave segment '/ps_e_0/SAXIGP4/HP2_QSPI' is being assigned into address space '/video/axi_vdma/Data_S2MM' at <0xC000_0000 [ 512M ]>. WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_M_AXI_S2MM_DATA_WIDTH(128) on '/video/axi_vdma' with propagated value(64). Command ignored INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc_0: Property SENSITIVITY = "NULL" for interrupt input 6 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary. WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc_0: Property SENSITIVITY = "NULL" for interrupt input 5 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary. INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /iop_pmod0/spi ####################################################################################### INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. ######################################################################################## INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /iop_pmod1/spi ####################################################################################### INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. ######################################################################################## WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e_0/S_AXI_HP0_FPD(1) and /shutdown_HP0_FPD/M_AXI(0) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e_0/S_AXI_HP0_FPD(1) and /shutdown_HP0_FPD/M_AXI(0) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e_0/S_AXI_HP2_FPD(1) and /shutdown_HP2_FPD/M_AXI(0) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e_0/S_AXI_HP2_FPD(1) and /shutdown_HP2_FPD/M_AXI(0) WARNING: [BD 41-237] Bus Interface property WUSER_WIDTH does not match between /ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1) WARNING: [BD 41-237] Bus Interface property RUSER_WIDTH does not match between /ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1) WARNING: [BD 41-237] Bus Interface property BUSER_WIDTH does not match between /ps_e_0/S_AXI_LPD(0) and /shutdown_LPD/M_AXI(1) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/i00_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M00_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/i00_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M00_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/i02_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M02_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/i02_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M02_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m11_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M03_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m11_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M03_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m12_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M04_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m12_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M04_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m13_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M05_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m13_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M05_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m14_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M06_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m14_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M06_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m15_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M07_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m15_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M07_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m08_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m08_couplers/auto_cc/M_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m08_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m08_couplers/auto_cc/M_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m09_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m09_couplers/auto_cc/M_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m09_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m09_couplers/auto_cc/M_AXI(16) WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m10_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m10_couplers/auto_cc/M_AXI(16) WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m10_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m10_couplers/auto_cc/M_AXI(16) validate_bd_design: Time (s): cpu = 00:01:02 ; elapsed = 00:01:02 . Memory (MB): peak = 8386.867 ; gain = 0.000 ; free physical = 9825 ; free virtual = 16429 Wrote : Wrote : update_compile_order -fileset sources_1 pwd /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base source ./build_bitstream.tcl # set overlay_name "base" # set design_name "base" # open_project ./${overlay_name}/${overlay_name}.xpr ERROR: [Coretcl 2-101] Project './base/base.xpr' is already open. launch_runs impl_1 -to_step write_bitstream -jobs 2 WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to pin: '/iop_pmod0/lmb/BRAM_PORTB_addr'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to pin: '/iop_pmod1/lmb/BRAM_PORTB_addr'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to pin: '/shutdown_HP0_FPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp2_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to pin: '/shutdown_HP0_FPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp2_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to pin: '/shutdown_HP2_FPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp4_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to pin: '/shutdown_HP2_FPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp4_rid'(6) - Only lower order bits will be connected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. VHDL Output written to : /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/synth/base.v WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to pin: '/iop_pmod0/lmb/BRAM_PORTB_addr'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to pin: '/iop_pmod1/lmb/BRAM_PORTB_addr'(16) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to pin: '/shutdown_LPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp6_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to pin: '/shutdown_LPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp6_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to pin: '/shutdown_HP0_FPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp2_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to pin: '/shutdown_HP0_FPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp2_rid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to pin: '/shutdown_HP2_FPD/m_axi_awid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to pin: '/ps_e_0/saxigp4_bid'(6) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to pin: '/shutdown_HP2_FPD/m_axi_arid'(1) - Only lower order bits will be connected. WARNING: [BD 41-2384] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to pin: '/ps_e_0/saxigp4_rid'(6) - Only lower order bits will be connected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. CRITICAL WARNING: [BD 41-2383] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to pin '/ps_e_0/emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. VHDL Output written to : /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/sim/base.v VHDL Output written to : /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hdl/base_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block address_remap_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/xbar . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_2 . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i00_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_0/base_auto_pc_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i00_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i02_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_1/base_auto_pc_1_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i02_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m07_couplers/auto_cc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_cc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_2/base_auto_pc_2_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_cc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_3/base_auto_pc_3_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_cc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_4/base_auto_pc_4_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m11_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m12_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m13_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_5/base_auto_pc_5_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m13_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m14_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_6/base_auto_pc_6_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m14_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m15_couplers/auto_ds . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_7/base_auto_pc_7_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m15_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m16_couplers/auto_cc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m18_couplers/auto_cc . INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/xbar . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_us . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s01_couplers/auto_us . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_8/base_auto_pc_8_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_pc . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_ooc.xdc' WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_us . INFO: [BD 41-1029] Generation completed for the IP Integrator block fmch_axi_iic . INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_btns . INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_leds . INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_sws . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/dff_en_reset_vector_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/gpio . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/iic . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intc . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr_concat . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/io_switch . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/dlmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/ilmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/lmb_bram . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/lmb_bram_if_cntlr . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/logic_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_bram_ctrl . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/xbar . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/rst_clk_wiz_1_100M . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/spi . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/timer . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/dff_en_reset_vector_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/gpio . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/iic . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intc . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intr . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intr_concat . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/io_switch . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/dlmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/ilmb_v10 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/lmb_bram . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/lmb_bram_if_cntlr . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/logic_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/mb . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/mb_bram_ctrl . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/xbar . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/rst_clk_wiz_1_100M . INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/spi . WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1_ooc.xdc' INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/timer . INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_intr_ack . INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_reset . INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod1_intr_ack . INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod1_reset . INFO: [BD 41-1029] Generation completed for the IP Integrator block mdm . INFO: [BD 41-1029] Generation completed for the IP Integrator block pmod0_buf . INFO: [BD 41-1029] Generation completed for the IP Integrator block pmod1_buf . INFO: [Common 17-14] Message 'BD 41-1029' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] base_ps_e_0_0: Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto. This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option. The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow. For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP2_FPD'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created. WARNING: [IP_Flow 19-650] IP license key 'v_hdmi@2017.10' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'v_hdmi@2017.10' is enabled with a Design_Linking license. Exporting to file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/hw_handoff/base_frontend_0.hwh Generated Block Design Tcl file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/hw_handoff/base_frontend_0_bd.tcl Generated Hardware Definition File /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/synth/base_frontend_0.hwdef WARNING: [IP_Flow 19-650] IP license key 'v_hdmi@2017.10' is enabled with a Design_Linking license. WARNING: [IP_Flow 19-650] IP license key 'v_hdmi@2017.10' is enabled with a Design_Linking license. Exporting to file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/hw_handoff/base_frontend_1.hwh Generated Block Design Tcl file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/hw_handoff/base_frontend_1_bd.tcl Generated Hardware Definition File /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/synth/base_frontend_1.hwdef Exporting to file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hw_handoff/base.hwh Generated Block Design Tcl file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hw_handoff/base_bd.tcl Generated Hardware Definition File /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/synth/base.hwdef CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the fileset sources_1. Resolution: With the gui up, review the source files in the Sources window. Use Add Sources to add any needed sources. If the files are disabled, enable them. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow. ERROR: [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top [current_fileset]). close_project pwd /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base source ./build_bitstream.tcl # set overlay_name "base" # set design_name "base" # open_project ./${overlay_name}/${overlay_name}.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hughesyang/Downloads/PYNQ-master/boards/ip'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hughesyang/tools/Vivado/2020.1/data/ip'. open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 10359.676 ; gain = 0.000 ; free physical = 9374 ; free virtual = 16247 # open_bd_design ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd Adding component instance block -- user.org:user:address_remap:1.0 - address_remap_0 Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - axi_intc_0 Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_0 Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_1 Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_2 Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0 Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_mem_intercon Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_mem_intercon_1 Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - fmch_axi_iic Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_btns Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_leds Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_sws Adding component instance block -- xilinx.com:user:dff_en_reset_vector:1.0 - dff_en_reset_vector_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - iic Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - intc Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - intr Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - intr_concat Adding component instance block -- xilinx.com:user:io_switch:1.1 - io_switch Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10 Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10 Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - lmb_bram_if_cntlr Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - logic_1 Adding component instance block -- xilinx.com:ip:microblaze:11.0 - mb Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - mb_bram_ctrl Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - microblaze_0_axi_periph Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m01_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m02_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m03_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m04_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m05_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m06_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m07_regslice Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - spi Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - timer WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod0/clk_100M(clk) and /iop_pmod0/dff_en_reset_vector_0/clk(undef) Adding component instance block -- xilinx.com:user:dff_en_reset_vector:1.0 - dff_en_reset_vector_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - iic Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - intc Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - intr Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - intr_concat Adding component instance block -- xilinx.com:user:io_switch:1.1 - io_switch Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10 Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10 Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - lmb_bram_if_cntlr Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - logic_1 Adding component instance block -- xilinx.com:ip:microblaze:11.0 - mb Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - mb_bram_ctrl Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - microblaze_0_axi_periph Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m01_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m02_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m03_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m04_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m05_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m06_regslice Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m07_regslice Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - spi Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - timer WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod1/clk_100M(clk) and /iop_pmod1/dff_en_reset_vector_0/clk(undef) Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_intr_ack Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_reset Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod1_intr_ack Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod1_reset Adding component instance block -- xilinx.com:ip:mdm:3.2 - mdm Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - pmod0_buf Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - pmod1_buf Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0 Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1 Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_2 Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_3 Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - ps_e_0 Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - reset_control Adding component instance block -- xilinx.com:ip:dfx_axi_shutdown_manager:1.0 - shutdown_HP0_FPD Adding component instance block -- xilinx.com:ip:dfx_axi_shutdown_manager:1.0 - shutdown_HP2_FPD Adding component instance block -- xilinx.com:ip:dfx_axi_shutdown_manager:1.0 - shutdown_LPD Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - vcc_const Adding component instance block -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - const_gnd Adding component instance block -- xilinx.com:hls:color_convert_2:1.0 - color_convert Adding component instance block -- xilinx.com:ip:v_hdmi_rx_ss:3.1 - frontend Adding component instance block -- xilinx.com:hls:pixel_pack_2:1.0 - pixel_pack Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - pixel_reorder Adding component instance block -- xilinx.com:ip:axis_register_slice:1.1 - rx_video_axis_reg_slice Adding component instance block -- xilinx.com:hls:color_convert_2:1.0 - color_convert Adding component instance block -- xilinx.com:ip:v_hdmi_tx_ss:3.1 - frontend Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - pixel_reorder Adding component instance block -- xilinx.com:hls:pixel_unpack_2:1.0 - pixel_unpack Adding component instance block -- xilinx.com:ip:axis_register_slice:1.1 - tx_video_axis_reg_slice Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - dru_ibufds_gt_odiv2 Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - gt_refclk_buf Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - vcc_const0 Adding component instance block -- xilinx.com:ip:vid_phy_controller:2.2 - vid_phy_controller Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat0 Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_1 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_0/dcm_locked(undef) WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_1/dcm_locked(undef) WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_2/dcm_locked(undef) WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_3/dcm_locked(undef) Successfully read diagram from BD file <./base/base.srcs/sources_1/bd/base/base.bd> WARNING: [BD 41-1731] Type mismatch between connected pins: /v_hdmi_rx/m_axis_video_aresetn_out(undef) and /v_vid_in_axi4s/aresetn(rst) WARNING: [BD 41-1731] Type mismatch between connected pins: /v_hdmi_tx/s_axis_video_aresetn_out(undef) and /v_axi4s_vid_out/aresetn(rst) open_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 10359.676 ; gain = 0.000 ; free physical = 9312 ; free virtual = 16185 # make_wrapper -files [get_files ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/${design_name}.bd] -top # add_files -norecurse ./${overlay_name}/${overlay_name}.srcs/sources_1/bd/${design_name}/hdl/${design_name}_wrapper.v # set_property top ${design_name}_wrapper [current_fileset] # import_files -fileset constrs_1 -norecurse ./vivado/constraints/${overlay_name}.xdc # update_compile_order -fileset sources_1 # set_property platform.default_output_type "sd_card" [current_project] # set_property platform.design_intent.embedded "true" [current_project] # set_property platform.design_intent.server_managed "false" [current_project] # set_property platform.design_intent.external_host "false" [current_project] # set_property platform.design_intent.datacenter "false" [current_project] # launch_runs impl_1 -to_step write_bitstream -jobs 4 [Wed Dec 9 22:20:48 2020] Launched base_auto_pc_0_synth_1, base_auto_ds_0_synth_1, base_xbar_0_synth_1, base_tier2_xbar_2_0_synth_1, base_auto_ds_1_synth_1, bd_20f1_v_hdmi_rx_0_synth_1, bd_20f1_inverter_1_0_synth_1, bd_20f1_v_vid_in_axi4s_0_synth_1, base_tx_video_axis_reg_slice_0_synth_1, base_vid_phy_controller_0_synth_1, base_frontend_0_synth_1, base_pixel_unpack_0_synth_1, base_color_convert_0_synth_1, base_m06_regslice_3_synth_1, base_mb_1_synth_1, base_m05_regslice_3_synth_1, base_m01_regslice_3_synth_1, base_gt_refclk_buf_0_synth_1, base_dru_ibufds_gt_odiv2_0_synth_1, base_pixel_reorder_1_synth_1, base_frontend_1_synth_1, base_color_convert_1_synth_1, base_rx_video_axis_reg_slice_0_synth_1, base_pixel_reorder_0_synth_1, base_pixel_pack_0_synth_1, base_axi_vdma_0_synth_1, base_shutdown_LPD_0_synth_1, base_shutdown_HP2_FPD_0_synth_1, base_shutdown_HP0_FPD_0_synth_1, base_reset_control_0_synth_1, base_ps_e_0_0_synth_1, base_proc_sys_reset_3_0_synth_1, base_proc_sys_reset_2_0_synth_1, base_proc_sys_reset_1_0_synth_1, base_proc_sys_reset_0_0_synth_1, base_pmod1_buf_0_synth_1, base_pmod0_buf_0_synth_1, base_mdm_0_synth_1, base_spi_1_synth_1, base_timer_1_synth_1, base_rst_clk_wiz_1_100M_1_synth_1, base_m07_regslice_3_synth_1, base_m04_regslice_3_synth_1, base_m03_regslice_3_synth_1, base_m02_regslice_3_synth_1, base_dff_en_reset_vector_0_1_synth_1, base_iic_1_synth_1, base_timer_0_synth_1, base_spi_0_synth_1, base_rst_clk_wiz_1_100M_0_synth_1, base_m06_regslice_2_synth_1, base_m05_regslice_2_synth_1, base_m04_regslice_2_synth_1, base_m03_regslice_2_synth_1, base_m02_regslice_2_synth_1, base_m01_regslice_2_synth_1, base_m00_regslice_2_synth_1, base_s00_regslice_2_synth_1, base_mb_0_synth_1, base_lmb_bram_if_cntlr_0_synth_1, base_gpio_0_synth_1, base_dff_en_reset_vector_0_0_synth_1, base_gpio_sws_0_synth_1, base_gpio_leds_0_synth_1, base_gpio_btns_0_synth_1, base_auto_pc_1_synth_1, base_auto_ds_3_synth_1, base_auto_pc_3_synth_1, base_auto_cc_3_synth_1, base_auto_ds_5_synth_1, base_auto_ds_6_synth_1, base_auto_ds_7_synth_1, base_auto_pc_6_synth_1, base_auto_ds_9_synth_1, base_auto_pc_7_synth_1, base_xbar_1_synth_1, base_auto_us_1_synth_1, base_auto_us_0_synth_1, base_dlmb_v10_0_synth_1, base_io_switch_0_synth_1, base_intr_0_synth_1, base_intc_0_synth_1, base_iic_0_synth_1, bd_e030_v_hdmi_tx_0_synth_1, bd_e030_v_tc_0_synth_1, bd_e030_v_axi4s_vid_out_0_synth_1, bd_e030_util_vector_logic_0_0_synth_1, bd_e030_axi_crossbar_0_synth_1, base_m00_regslice_3_synth_1, base_s00_regslice_3_synth_1, base_xbar_3_synth_1, base_mb_bram_ctrl_1_synth_1, base_lmb_bram_1_synth_1, base_ilmb_v10_1_synth_1, base_io_switch_1_synth_1, base_dlmb_v10_1_synth_1, base_gpio_1_synth_1, base_auto_cc_0_synth_1, base_tier2_xbar_1_0_synth_1, base_axi_intc_0_0_synth_1, base_tier2_xbar_0_0_synth_1, base_address_remap_0_0_synth_1, base_auto_pc_5_synth_1, base_auto_cc_2_synth_1, base_auto_ds_4_synth_1, base_auto_ds_2_synth_1, base_auto_cc_1_synth_1, base_auto_pc_2_synth_1, base_intr_1_synth_1, base_lmb_bram_if_cntlr_1_synth_1, base_intc_1_synth_1, base_xbar_2_synth_1, base_m07_regslice_2_synth_1, base_lmb_bram_0_synth_1, base_mb_bram_ctrl_0_synth_1, base_auto_pc_8_synth_1, base_fmch_axi_iic_0_synth_1, base_auto_pc_4_synth_1, base_auto_cc_4_synth_1, base_auto_ds_8_synth_1, base_auto_us_2_synth_1, base_auto_cc_5_synth_1, base_ilmb_v10_0_synth_1, synth_1... Run output will be captured here: base_auto_pc_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_pc_0_synth_1/runme.log base_auto_ds_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_ds_0_synth_1/runme.log base_xbar_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_xbar_0_synth_1/runme.log base_tier2_xbar_2_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_tier2_xbar_2_0_synth_1/runme.log base_auto_ds_1_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_ds_1_synth_1/runme.log bd_20f1_v_hdmi_rx_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/bd_20f1_v_hdmi_rx_0_synth_1/runme.log bd_20f1_inverter_1_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/bd_20f1_inverter_1_0_synth_1/runme.log bd_20f1_v_vid_in_axi4s_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/bd_20f1_v_vid_in_axi4s_0_synth_1/runme.log base_tx_video_axis_reg_slice_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_tx_video_axis_reg_slice_0_synth_1/runme.log base_vid_phy_controller_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_vid_phy_controller_0_synth_1/runme.log base_frontend_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_frontend_0_synth_1/runme.log base_pixel_unpack_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_pixel_unpack_0_synth_1/runme.log base_color_convert_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_color_convert_0_synth_1/runme.log base_m06_regslice_3_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_m06_regslice_3_synth_1/runme.log base_mb_1_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_mb_1_synth_1/runme.log base_m05_regslice_3_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_m05_regslice_3_synth_1/runme.log base_m01_regslice_3_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_m01_regslice_3_synth_1/runme.log base_gt_refclk_buf_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_gt_refclk_buf_0_synth_1/runme.log base_dru_ibufds_gt_odiv2_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_dru_ibufds_gt_odiv2_0_synth_1/runme.log base_pixel_reorder_1_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_pixel_reorder_1_synth_1/runme.log base_frontend_1_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_frontend_1_synth_1/runme.log base_color_convert_1_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_color_convert_1_synth_1/runme.log base_rx_video_axis_reg_slice_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_rx_video_axis_reg_slice_0_synth_1/runme.log base_pixel_reorder_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_pixel_reorder_0_synth_1/runme.log base_pixel_pack_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_pixel_pack_0_synth_1/runme.log base_axi_vdma_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_axi_vdma_0_synth_1/runme.log base_shutdown_LPD_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_shutdown_LPD_0_synth_1/runme.log base_shutdown_HP2_FPD_0_synth_1: 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/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_xbar_2_synth_1/runme.log base_m07_regslice_2_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_m07_regslice_2_synth_1/runme.log base_lmb_bram_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_lmb_bram_0_synth_1/runme.log base_mb_bram_ctrl_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_mb_bram_ctrl_0_synth_1/runme.log base_auto_pc_8_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_pc_8_synth_1/runme.log base_fmch_axi_iic_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_fmch_axi_iic_0_synth_1/runme.log base_auto_pc_4_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_pc_4_synth_1/runme.log base_auto_cc_4_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_cc_4_synth_1/runme.log base_auto_ds_8_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_ds_8_synth_1/runme.log base_auto_us_2_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_us_2_synth_1/runme.log base_auto_cc_5_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_auto_cc_5_synth_1/runme.log base_ilmb_v10_0_synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/base_ilmb_v10_0_synth_1/runme.log synth_1: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/synth_1/runme.log [Wed Dec 9 22:21:04 2020] Launched impl_1... Run output will be captured here: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/runme.log launch_runs: Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 10359.676 ; gain = 0.000 ; free physical = 6986 ; free virtual = 13874 # wait_on_run impl_1 [Wed Dec 9 22:21:04 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:09 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:14 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:19 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:30 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:40 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:21:51 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:22:01 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:22:22 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:22:42 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:23:03 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:23:23 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:24:04 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:24:45 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:25:27 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:26:08 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:27:31 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:28:53 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:30:16 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:31:38 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:34:22 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:37:06 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:39:50 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:42:30 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:47:53 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:53:16 2020] Waiting for impl_1 to finish... [Wed Dec 9 22:58:40 2020] Waiting for impl_1 to finish... [Wed Dec 9 23:04:02 2020] Waiting for impl_1 to finish... [Wed Dec 9 23:14:43 2020] Waiting for impl_1 to finish... [Wed Dec 9 23:25:26 2020] Waiting for impl_1 to finish... [Wed Dec 9 23:36:10 2020] Waiting for impl_1 to finish... [Wed Dec 9 23:46:53 2020] Waiting for impl_1 to finish... [Thu Dec 10 00:08:15 2020] Waiting for impl_1 to finish... *** Running vivado with args -log base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source base_wrapper.tcl -notrace ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source base_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/hughesyang/Downloads/PYNQ-master/boards/ip'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hughesyang/tools/Vivado/2020.1/data/ip'. update_ip_catalog: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2227.477 ; gain = 0.000 ; free physical = 7949 ; free virtual = 15379 add_files: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2243.488 ; gain = 16.012 ; free physical = 7859 ; free virtual = 15289 Command: link_design -top base_wrapper -part xczu7ev-ffvc1156-2-e Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_address_remap_0_0/base_address_remap_0_0.dcp' for cell 'base_i/address_remap_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.dcp' for cell 'base_i/axi_intc_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0.dcp' for cell 'base_i/fmch_axi_iic' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.dcp' for cell 'base_i/gpio_btns' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.dcp' for cell 'base_i/gpio_leds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.dcp' for cell 'base_i/gpio_sws' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.dcp' for cell 'base_i/mdm' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0.dcp' for cell 'base_i/pmod0_buf' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0.dcp' for cell 'base_i/pmod1_buf' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.dcp' for cell 'base_i/proc_sys_reset_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.dcp' for cell 'base_i/proc_sys_reset_1' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.dcp' for cell 'base_i/proc_sys_reset_2' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.dcp' for cell 'base_i/proc_sys_reset_3' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.dcp' for cell 'base_i/ps_e_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.dcp' for cell 'base_i/reset_control' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_HP0_FPD_0/base_shutdown_HP0_FPD_0.dcp' for cell 'base_i/shutdown_HP0_FPD' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_HP2_FPD_0/base_shutdown_HP2_FPD_0.dcp' for cell 'base_i/shutdown_HP2_FPD' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_LPD_0/base_shutdown_LPD_0.dcp' for cell 'base_i/shutdown_LPD' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_0_0/base_tier2_xbar_0_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_1_0/base_tier2_xbar_1_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_1' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_2_0/base_tier2_xbar_2_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_2' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_0/base_xbar_0.dcp' for cell 'base_i/axi_interconnect/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0.dcp' for cell 'base_i/axi_interconnect/i00_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_0/base_auto_pc_0.dcp' for cell 'base_i/axi_interconnect/i00_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1.dcp' for cell 'base_i/axi_interconnect/i02_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_1/base_auto_pc_1.dcp' for cell 'base_i/axi_interconnect/i02_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0.dcp' for cell 'base_i/axi_interconnect/m07_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_2/base_auto_pc_2.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_3/base_auto_pc_3.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_4/base_auto_pc_4.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5.dcp' for cell 'base_i/axi_interconnect/m11_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6.dcp' for cell 'base_i/axi_interconnect/m12_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7.dcp' for cell 'base_i/axi_interconnect/m13_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_5/base_auto_pc_5.dcp' for cell 'base_i/axi_interconnect/m13_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8.dcp' for cell 'base_i/axi_interconnect/m14_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_6/base_auto_pc_6.dcp' for cell 'base_i/axi_interconnect/m14_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9.dcp' for cell 'base_i/axi_interconnect/m15_couplers/auto_ds' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_7/base_auto_pc_7.dcp' for cell 'base_i/axi_interconnect/m15_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4.dcp' for cell 'base_i/axi_interconnect/m16_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5.dcp' for cell 'base_i/axi_interconnect/m18_couplers/auto_cc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_1/base_xbar_1.dcp' for cell 'base_i/axi_interconnect_0/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_8/base_auto_pc_8.dcp' for cell 'base_i/axi_interconnect_0/m00_couplers/auto_pc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0.dcp' for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1.dcp' for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2.dcp' for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dff_en_reset_vector_0_0/base_dff_en_reset_vector_0_0.dcp' for cell 'base_i/iop_pmod0/dff_en_reset_vector_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.dcp' for cell 'base_i/iop_pmod0/gpio' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0.dcp' for cell 'base_i/iop_pmod0/iic' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.dcp' for cell 'base_i/iop_pmod0/intc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.dcp' for cell 'base_i/iop_pmod0/intr' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_io_switch_0/base_io_switch_0.dcp' for cell 'base_i/iop_pmod0/io_switch' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.dcp' for cell 'base_i/iop_pmod0/mb' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_bram_ctrl_0/base_mb_bram_ctrl_0.dcp' for cell 'base_i/iop_pmod0/mb_bram_ctrl' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.dcp' for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.dcp' for cell 'base_i/iop_pmod0/spi' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.dcp' for cell 'base_i/iop_pmod0/timer' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_0/base_dlmb_v10_0.dcp' for cell 'base_i/iop_pmod0/lmb/dlmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_0/base_ilmb_v10_0.dcp' for cell 'base_i/iop_pmod0/lmb/ilmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_0/base_lmb_bram_0.dcp' for cell 'base_i/iop_pmod0/lmb/lmb_bram' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_if_cntlr_0/base_lmb_bram_if_cntlr_0.dcp' for cell 'base_i/iop_pmod0/lmb/lmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_2/base_xbar_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dff_en_reset_vector_0_1/base_dff_en_reset_vector_0_1.dcp' for cell 'base_i/iop_pmod1/dff_en_reset_vector_0' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.dcp' for cell 'base_i/iop_pmod1/gpio' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1.dcp' for cell 'base_i/iop_pmod1/iic' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.dcp' for cell 'base_i/iop_pmod1/intc' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.dcp' for cell 'base_i/iop_pmod1/intr' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_io_switch_1/base_io_switch_1.dcp' for cell 'base_i/iop_pmod1/io_switch' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.dcp' for cell 'base_i/iop_pmod1/mb' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_bram_ctrl_1/base_mb_bram_ctrl_1.dcp' for cell 'base_i/iop_pmod1/mb_bram_ctrl' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.dcp' for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.dcp' for cell 'base_i/iop_pmod1/spi' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.dcp' for cell 'base_i/iop_pmod1/timer' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_1/base_dlmb_v10_1.dcp' for cell 'base_i/iop_pmod1/lmb/dlmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_1/base_ilmb_v10_1.dcp' for cell 'base_i/iop_pmod1/lmb/ilmb_v10' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_1/base_lmb_bram_1.dcp' for cell 'base_i/iop_pmod1/lmb/lmb_bram' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_if_cntlr_1/base_lmb_bram_if_cntlr_1.dcp' for cell 'base_i/iop_pmod1/lmb/lmb_bram_if_cntlr' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_3/base_xbar_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/xbar' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice' INFO: [Project 1-454] Reading design checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice' INFO: [Common 17-14] Message 'Project 1-454' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3036.891 ; gain = 0.000 ; free physical = 6651 ; free virtual = 14082 INFO: [Netlist 29-17] Analyzing 2608 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. INFO: [Common 17-14] Message 'Constraints 18-550' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.xdc] for cell 'base_i/axi_intc_0/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.xdc] for cell 'base_i/axi_intc_0/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0_board.xdc] for cell 'base_i/fmch_axi_iic/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0_board.xdc] for cell 'base_i/fmch_axi_iic/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0_board.xdc] for cell 'base_i/gpio_btns/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0_board.xdc] for cell 'base_i/gpio_btns/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.xdc] for cell 'base_i/gpio_btns/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.xdc] for cell 'base_i/gpio_btns/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0_board.xdc] for cell 'base_i/gpio_leds/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0_board.xdc] for cell 'base_i/gpio_leds/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.xdc] for cell 'base_i/gpio_leds/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.xdc] for cell 'base_i/gpio_leds/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0_board.xdc] for cell 'base_i/gpio_sws/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0_board.xdc] for cell 'base_i/gpio_sws/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.xdc] for cell 'base_i/gpio_sws/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.xdc] for cell 'base_i/gpio_sws/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0_board.xdc] for cell 'base_i/iop_pmod0/gpio/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0_board.xdc] for cell 'base_i/iop_pmod0/gpio/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.xdc] for cell 'base_i/iop_pmod0/gpio/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.xdc] for cell 'base_i/iop_pmod0/gpio/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0_board.xdc] for cell 'base_i/iop_pmod0/iic/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0_board.xdc] for cell 'base_i/iop_pmod0/iic/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.xdc] for cell 'base_i/iop_pmod0/intc/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.xdc] for cell 'base_i/iop_pmod0/intc/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0_board.xdc] for cell 'base_i/iop_pmod0/intr/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0_board.xdc] for cell 'base_i/iop_pmod0/intr/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.xdc] for cell 'base_i/iop_pmod0/intr/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.xdc] for cell 'base_i/iop_pmod0/intr/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.xdc] for cell 'base_i/iop_pmod0/mb/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.xdc] for cell 'base_i/iop_pmod0/mb/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0_board.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0_board.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_board.xdc] for cell 'base_i/iop_pmod0/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_board.xdc] for cell 'base_i/iop_pmod0/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.xdc] for cell 'base_i/iop_pmod0/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.xdc] for cell 'base_i/iop_pmod0/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.xdc] for cell 'base_i/iop_pmod0/timer/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.xdc] for cell 'base_i/iop_pmod0/timer/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1_board.xdc] for cell 'base_i/iop_pmod1/gpio/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1_board.xdc] for cell 'base_i/iop_pmod1/gpio/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.xdc] for cell 'base_i/iop_pmod1/gpio/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.xdc] for cell 'base_i/iop_pmod1/gpio/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1_board.xdc] for cell 'base_i/iop_pmod1/iic/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1_board.xdc] for cell 'base_i/iop_pmod1/iic/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.xdc] for cell 'base_i/iop_pmod1/intc/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.xdc] for cell 'base_i/iop_pmod1/intc/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1_board.xdc] for cell 'base_i/iop_pmod1/intr/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1_board.xdc] for cell 'base_i/iop_pmod1/intr/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.xdc] for cell 'base_i/iop_pmod1/intr/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.xdc] for cell 'base_i/iop_pmod1/intr/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.xdc] for cell 'base_i/iop_pmod1/mb/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.xdc] for cell 'base_i/iop_pmod1/mb/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1_board.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1_board.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_board.xdc] for cell 'base_i/iop_pmod1/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_board.xdc] for cell 'base_i/iop_pmod1/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.xdc] for cell 'base_i/iop_pmod1/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.xdc] for cell 'base_i/iop_pmod1/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.xdc] for cell 'base_i/iop_pmod1/timer/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.xdc] for cell 'base_i/iop_pmod1/timer/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc] for cell 'base_i/mdm/U0' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc:51] get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 4209.375 ; gain = 467.160 ; free physical = 5234 ; free virtual = 12687 Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc] for cell 'base_i/mdm/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0_board.xdc] for cell 'base_i/pmod0_buf/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0_board.xdc] for cell 'base_i/pmod0_buf/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0_board.xdc] for cell 'base_i/pmod1_buf/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0_board.xdc] for cell 'base_i/pmod1_buf/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0_board.xdc] for cell 'base_i/proc_sys_reset_0/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0_board.xdc] for cell 'base_i/proc_sys_reset_0/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.xdc] for cell 'base_i/proc_sys_reset_0/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.xdc] for cell 'base_i/proc_sys_reset_0/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0_board.xdc] for cell 'base_i/proc_sys_reset_1/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0_board.xdc] for cell 'base_i/proc_sys_reset_1/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.xdc] for cell 'base_i/proc_sys_reset_1/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.xdc] for cell 'base_i/proc_sys_reset_1/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0_board.xdc] for cell 'base_i/proc_sys_reset_2/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0_board.xdc] for cell 'base_i/proc_sys_reset_2/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.xdc] for cell 'base_i/proc_sys_reset_2/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.xdc] for cell 'base_i/proc_sys_reset_2/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0_board.xdc] for cell 'base_i/proc_sys_reset_3/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0_board.xdc] for cell 'base_i/proc_sys_reset_3/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.xdc] for cell 'base_i/proc_sys_reset_3/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.xdc] for cell 'base_i/proc_sys_reset_3/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.xdc] for cell 'base_i/ps_e_0/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.xdc] for cell 'base_i/ps_e_0/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0_board.xdc] for cell 'base_i/reset_control/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0_board.xdc] for cell 'base_i/reset_control/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.xdc] for cell 'base_i/reset_control/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.xdc] for cell 'base_i/reset_control/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc] for cell 'base_i/video/axi_vdma/U0' WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:68] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:72] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:76] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:80] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:84] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:88] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:92] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:96] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:100] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:104] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:108] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:192] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:196] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:200] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:204] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:208] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:212] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:216] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:220] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc] for cell 'base_i/video/axi_vdma/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dru_ibufds_gt_odiv2_0/base_dru_ibufds_gt_odiv2_0_board.xdc] for cell 'base_i/video/phy/dru_ibufds_gt_odiv2/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dru_ibufds_gt_odiv2_0/base_dru_ibufds_gt_odiv2_0_board.xdc] for cell 'base_i/video/phy/dru_ibufds_gt_odiv2/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gt_refclk_buf_0/base_gt_refclk_buf_0_board.xdc] for cell 'base_i/video/phy/gt_refclk_buf/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gt_refclk_buf_0/base_gt_refclk_buf_0_board.xdc] for cell 'base_i/video/phy/gt_refclk_buf/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/ip_0/synth/base_vid_phy_controller_0_gtwrapper.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_wrapper_inst/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/ip_0/synth/base_vid_phy_controller_0_gtwrapper.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_wrapper_inst/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/vid_phy_controller_xdc.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/vid_phy_controller_xdc.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/constrs_1/imports/constraints/base.xdc] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/constrs_1/imports/constraints/base.xdc] Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0_clocks.xdc] for cell 'base_i/axi_intc_0/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0_clocks.xdc] for cell 'base_i/axi_intc_0/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_clocks.xdc] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_clocks.xdc] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_clocks.xdc] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_clocks.xdc] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst' WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:7] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:13] WARNING: [Vivado 12-180] No cells matched '*gen_clock_conv.gen_async_conv.asyncfifo_axi*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:17] WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical * -filter {(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)}'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:17] WARNING: [Vivado_Tcl 4-939] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:17] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_clocks.xdc] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_clocks.xdc] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_clocks.xdc] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_clocks.xdc] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_clocks.xdc] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_clocks.xdc] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_clocks.xdc] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_clocks.xdc] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_clocks.xdc] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_clocks.xdc] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst' WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:7] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:13] WARNING: [Vivado 12-180] No cells matched '*gen_clock_conv.gen_async_conv.asyncfifo_axi*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:17] WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical * -filter {(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)}'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:17] WARNING: [Vivado_Tcl 4-939] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:17] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst' WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:7] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:13] WARNING: [Vivado 12-180] No cells matched '*gen_clock_conv.gen_async_conv.asyncfifo_axi*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:17] WARNING: [Vivado 12-508] No pins matched 'get_pins -hierarchical * -filter {(NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg*/PRE) || (NAME=~*gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.g*_ch.g*ch2.axi_*/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg*/PRE)}'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:17] WARNING: [Vivado_Tcl 4-939] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:17] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_clocks.xdc] for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_clocks.xdc] for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_clocks.xdc] for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_clocks.xdc] for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_clocks.xdc] for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_clocks.xdc] for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0_clocks.xdc] for cell 'base_i/iop_pmod0/intc/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0_clocks.xdc] for cell 'base_i/iop_pmod0/intc/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_clocks.xdc] for cell 'base_i/iop_pmod0/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_clocks.xdc] for cell 'base_i/iop_pmod0/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1_clocks.xdc] for cell 'base_i/iop_pmod1/intc/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1_clocks.xdc] for cell 'base_i/iop_pmod1/intc/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' WARNING: [Vivado 12-180] No cells matched '.*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc:10] WARNING: [Vivado 12-508] No pins matched 'get_pins -filter REF_PIN_NAME=~CLR -of_objects [get_cells -hierarchical -regexp .*15.*_multi/.*/common.srl_fifo_0/asyncclear_.*]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc:10] WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-7' -to list should not be empty. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc:10] Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_clocks.xdc] for cell 'base_i/iop_pmod1/spi/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_clocks.xdc] for cell 'base_i/iop_pmod1/spi/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0_clocks.xdc] for cell 'base_i/video/axi_vdma/U0' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0_clocks.xdc] for cell 'base_i/video/axi_vdma/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_0/bd_20f1_v_hdmi_rx_0_core.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_0/bd_20f1_v_hdmi_rx_0_core.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_1/bd_20f1_v_vid_in_axi4s_0_clocks.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_1/bd_20f1_v_vid_in_axi4s_0_clocks.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rx_video_axis_reg_slice_0/base_rx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_in/rx_video_axis_reg_slice/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rx_video_axis_reg_slice_0/base_rx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_in/rx_video_axis_reg_slice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_0/bd_e030_v_hdmi_tx_0_core.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_0/bd_e030_v_hdmi_tx_0_core.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_tc/U0' WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of [get_ports -scoped_to_current_instance clk]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:2] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:2] CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:5] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:6] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:6] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_tc/U0' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_2/bd_e030_v_axi4s_vid_out_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_2/bd_e030_v_axi4s_vid_out_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tx_video_axis_reg_slice_0/base_tx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_out/tx_video_axis_reg_slice/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tx_video_axis_reg_slice_0/base_tx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_out/tx_video_axis_reg_slice/inst' Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/base_vid_phy_controller_0_clocks.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' Finished Parsing XDC File [/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/base_vid_phy_controller_0_clocks.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_FREQ_CAP_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_FREQ_CAP_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_FREQ_CAP_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_FREQ_CAP_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_FREQ_CAP_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_FREQ_CAP_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_VERSION_in_sync_b0gt0inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_VERSION_in_sync_b0gt0inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_drp_reset_RST_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_drp_reset_RST_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/LRST_XPM_ASYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/LRST_XPM_ASYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/LRST_XPM_ASYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/LRST_XPM_ASYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/LRST_XPM_ASYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/LRST_XPM_ASYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt2inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt2inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b02_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b02_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.rxoutclk_mmcm0_i/rx_mmcm_locked_xpm' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.rxoutclk_mmcm0_i/rx_mmcm_locked_xpm' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.txoutclk_mmcm0_i/tx_mmcm_locked_xpm' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.txoutclk_mmcm0_i/tx_mmcm_locked_xpm' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TX_LOCK_CAP_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TX_LOCK_CAP_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RUN_SYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RUN_SYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RUN_SYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RUN_SYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RUN_SYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RUN_SYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' of design 'design_1' [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_mmcm_drp_locked_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_mmcm_drp_locked_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_tx_done_out_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_tx_done_out_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_rx_done_out_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_rx_done_out_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_done_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_done_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_reset_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_reset_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_start_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_start_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_error_b0_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_error_b0_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt0inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt0inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b00_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b00_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt1inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt1inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b01_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b01_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_PKT_ECC_ERR_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_PKT_ECC_ERR_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_CLR_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_CLR_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LRST_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LRST_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_ALN_LOCK_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_ALN_LOCK_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/LCLK_TS_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/LCLK_TS_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.VCLK_VGB_RST_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.VCLK_VGB_RST_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_SCRM_EN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_SCRM_EN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_LNK_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_LNK_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_GCP_CD_CHG_ACK_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_GCP_CD_CHG_ACK_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_HDMI_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_HDMI_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CHG_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CHG_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_PKT_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_PKT_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_FLUSH_CLR_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_FLUSH_CLR_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_PRO_UPD_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_PRO_UPD_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_ACT_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_ACT_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VID_BRDG_OVERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VID_BRDG_OVERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG2_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG2_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG1_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG1_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG0_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/WA_CHG0_CDC_INST/REQ_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LCLK_VID_VSYNC_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LCLK_VID_VSYNC_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/VCLK_CTRL_FLD_POL_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/VCLK_CTRL_FLD_POL_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_HS_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_HS_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_EN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_EN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_LNK_RST_CAP_INST/XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_LNK_RST_CAP_INST/XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FIFO_FLUSH_CNT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CD_INST/DET_SYNC_INST/XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CD_INST/DET_SYNC_INST/XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_REMAP_OVERFLOW_INST/xpm_cdc_single_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_REMAP_OVERFLOW_INST/xpm_cdc_single_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_RESET_PULSE_INST/xpm_cdc_single_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_RESET_PULSE_INST/xpm_cdc_single_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/PIO_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/PIO_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_NOISE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_NOISE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_VS_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_VS_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_LOCKED_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_LOCKED_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_UNDERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_UNDERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_CLEARAVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_CLEARAVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SCLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SCLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_VID_VS_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_VID_VS_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_SCRM_INST/gen_single.(null)[0].XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_SCRM_INST/gen_single.(null)[0].XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_WO_ARB.VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/HPD_INST/HPD_CAP_INST/XPM_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/HPD_INST/HPD_CAP_INST/XPM_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/M_AXIS_VIDEO_RST_CDC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/M_AXIS_VIDEO_RST_CDC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/VIDEO_RST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/VIDEO_RST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SRST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SRST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ARST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ARST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VRST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VRST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_RST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_RST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/S_AXIS_VIDEO_RST_CDC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/S_AXIS_VIDEO_RST_CDC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/LRST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/LRST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/VIDEO_RST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/VIDEO_RST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/AXIS_RST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/AXIS_RST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SRST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SRST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ARST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ARST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VRST_INST/XPM_RST_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VRST_INST/XPM_RST_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' Finished Sourcing Tcl File [/home/hughesyang/tools/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: [Constraints 18-5572] Instance base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Generating merged BMM file for the design top 'base_wrapper'... INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/data/mb_bootloop_le.elf /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/data/mb_bootloop_le.elf Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4245.441 ; gain = 0.000 ; free physical = 5354 ; free virtual = 12808 INFO: [Project 1-111] Unisim Transformation Summary: A total of 899 instances were transformed. DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 39 instances IBUF => IBUF (IBUFCTRL, INBUF): 12 instances IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 22 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 160 instances OBUFTDS => OBUFTDS: 2 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 32 instances RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 449 instances RAM64M8 => RAM64M8 (RAMD64E(x8)): 133 instances RAM64X1D => RAM64X1D (RAMD64E(x2)): 48 instances RAM64X1S => RAM64X1S (RAMS64E): 2 instances 193 Infos, 244 Warnings, 3 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:02:01 ; elapsed = 00:04:06 . Memory (MB): peak = 4245.441 ; gain = 2001.953 ; free physical = 5353 ; free virtual = 12808 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 4261.398 ; gain = 15.957 ; free physical = 5333 ; free virtual = 12788 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 13480fda3 Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4261.398 ; gain = 0.000 ; free physical = 5187 ; free virtual = 12642 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 197 inverter(s) to 14939 load pin(s). INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_in/color_convert/inst/ret_V_10_reg_1734_reg INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_out/color_convert/inst/ret_V_10_reg_1734_reg INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1affedecb Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5171 ; free virtual = 12627 INFO: [Opt 31-389] Phase Retarget created 548 cells and removed 1547 cells INFO: [Opt 31-1021] In phase Retarget, 354 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 10 inverter(s) to 10 load pin(s). Phase 2 Constant propagation | Checksum: 1885ba0fd Time (s): cpu = 00:00:15 ; elapsed = 00:00:12 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5171 ; free virtual = 12626 INFO: [Opt 31-389] Phase Constant propagation created 734 cells and removed 3672 cells INFO: [Opt 31-1021] In phase Constant propagation, 673 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 1b40ecf6e Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5174 ; free virtual = 12629 INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 15375 cells INFO: [Opt 31-1021] In phase Sweep, 1504 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-194] Inserted BUFG base_i/mdm/U0/Use_E2.BSCAN_I/Dbg_Update_0_BUFG_inst to drive 53 load(s) on clock net base_i/mdm/U0/Use_E2.BSCAN_I/Dbg_Update_0_BUFGCE INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets INFO: [Opt 31-1077] Phase BUFG optimization inserted 0 global clock buffer(s) for CLOCK_LOW_FANOUT. INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells Phase 4 BUFG optimization | Checksum: 1ec2ac89b Time (s): cpu = 00:00:32 ; elapsed = 00:00:29 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5176 ; free virtual = 12631 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 2 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 1ec2ac89b Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5175 ; free virtual = 12631 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1b80fac1a Time (s): cpu = 00:00:35 ; elapsed = 00:00:32 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5170 ; free virtual = 12625 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 469 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 548 | 1547 | 354 | | Constant propagation | 734 | 3672 | 673 | | Sweep | 6 | 15375 | 1504 | | BUFG optimization | 1 | 2 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 469 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.35 . Memory (MB): peak = 4448.035 ; gain = 0.000 ; free physical = 5173 ; free virtual = 12629 Ending Logic Optimization Task | Checksum: eb7b5d93 Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 4448.035 ; gain = 35.676 ; free physical = 5173 ; free virtual = 12629 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 63 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 23 WE to EN ports Number of BRAM Ports augmented: 4 newly gated: 23 Total Ports: 126 Ending PowerOpt Patch Enables Task | Checksum: e93bfafb Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4431 ; free virtual = 12020 Ending Power Optimization Task | Checksum: e93bfafb Time (s): cpu = 00:01:39 ; elapsed = 00:01:01 . Memory (MB): peak = 5902.512 ; gain = 1454.477 ; free physical = 4538 ; free virtual = 12127 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: e93bfafb Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4538 ; free virtual = 12127 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4538 ; free virtual = 12127 Ending Netlist Obfuscation Task | Checksum: c579e2f3 Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4538 ; free virtual = 12127 INFO: [Common 17-83] Releasing license: Implementation 226 Infos, 244 Warnings, 3 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:02:41 ; elapsed = 00:01:55 . Memory (MB): peak = 5902.512 ; gain = 1657.070 ; free physical = 4538 ; free virtual = 12127 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.04 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4399 ; free virtual = 11993 INFO: [Common 17-1381] The checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:38 . Memory (MB): peak = 5902.512 ; gain = 0.000 ; free physical = 4352 ; free virtual = 11978 INFO: [runtcl-4] Executing : report_drc -file base_wrapper_drc_opted.rpt -pb base_wrapper_drc_opted.pb -rpx base_wrapper_drc_opted.rpx Command: report_drc -file base_wrapper_drc_opted.rpt -pb base_wrapper_drc_opted.pb -rpx base_wrapper_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 5918.520 ; gain = 16.008 ; free physical = 4326 ; free virtual = 11952 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4322 ; free virtual = 11948 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b746c758 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4322 ; free virtual = 11948 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4322 ; free virtual = 11948 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 86c128d6 Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4311 ; free virtual = 11937 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 11de2e4e8 Time (s): cpu = 00:01:02 ; elapsed = 00:00:40 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4094 ; free virtual = 11721 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 11de2e4e8 Time (s): cpu = 00:01:03 ; elapsed = 00:00:41 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4094 ; free virtual = 11720 Phase 1 Placer Initialization | Checksum: 11de2e4e8 Time (s): cpu = 00:01:03 ; elapsed = 00:00:41 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4087 ; free virtual = 11713 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1.1 Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement Phase 2.1.1.1 PBP: Partition Driven Placement | Checksum: c215916c Time (s): cpu = 00:02:19 ; elapsed = 00:01:14 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4024 ; free virtual = 11651 Phase 2.1.1.2 PBP: Clock Region Placement Phase 2.1.1.2 PBP: Clock Region Placement | Checksum: 1571a9017 Time (s): cpu = 00:02:22 ; elapsed = 00:01:17 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4014 ; free virtual = 11640 Phase 2.1.1.3 PBP: Discrete Incremental Phase 2.1.1.3 PBP: Discrete Incremental | Checksum: a1a686d9 Time (s): cpu = 00:02:22 ; elapsed = 00:01:17 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4012 ; free virtual = 11639 Phase 2.1.1.4 PBP: Compute Congestion Phase 2.1.1.4 PBP: Compute Congestion | Checksum: a1a686d9 Time (s): cpu = 00:02:24 ; elapsed = 00:01:18 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3988 ; free virtual = 11615 Phase 2.1.1.5 PBP: Macro Placement Phase 2.1.1.5 PBP: Macro Placement | Checksum: ec16f956 Time (s): cpu = 00:02:24 ; elapsed = 00:01:19 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3988 ; free virtual = 11615 Phase 2.1.1.6 PBP: UpdateTiming Phase 2.1.1.6 PBP: UpdateTiming | Checksum: a9a6ba58 Time (s): cpu = 00:02:29 ; elapsed = 00:01:24 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3965 ; free virtual = 11592 Phase 2.1.1.7 PBP: Add part constraints Phase 2.1.1.7 PBP: Add part constraints | Checksum: a9a6ba58 Time (s): cpu = 00:02:29 ; elapsed = 00:01:24 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3965 ; free virtual = 11592 Phase 2.1.1 Partition Driven Placement | Checksum: a9a6ba58 Time (s): cpu = 00:02:29 ; elapsed = 00:01:24 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3991 ; free virtual = 11618 Phase 2.1 Floorplanning | Checksum: a9a6ba58 Time (s): cpu = 00:02:29 ; elapsed = 00:01:24 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3991 ; free virtual = 11618 Phase 2.2 Global Placement Core Phase 2.2.1 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 4 LUTNM shape to break, 2789 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 4, two critical 0, total 4, new lutff created 0 INFO: [Physopt 32-775] End 1 Pass. Optimized 1072 nets or cells. Created 4 new cells, deleted 1068 existing cells and moved 0 existing cell WARNING: [Physopt 32-894] Found a constraint with the -through option on pin base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. INFO: [Physopt 32-81] Processed net base_i/proc_sys_reset_1/U0/peripheral_aresetn[0]. Replicated 8 times. WARNING: [Physopt 32-894] Found a constraint with the -through option on pin base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst or the net immediately connecting to the pin. This constraint will block optimizations for this and all downstream leaf pins. INFO: [Physopt 32-232] Optimized 1 net. Created 8 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 8 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.23 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3963 ; free virtual = 11592 INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3965 ; free virtual = 11594 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 4 | 1068 | 1072 | 0 | 1 | 00:00:03 | | Very High Fanout | 8 | 0 | 1 | 0 | 1 | 00:00:02 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 12 | 1068 | 1073 | 0 | 8 | 00:00:06 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2.1 Physical Synthesis In Placer | Checksum: 232548816 Time (s): cpu = 00:04:58 ; elapsed = 00:03:06 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3963 ; free virtual = 11593 Phase 2.2 Global Placement Core | Checksum: 17b775e08 Time (s): cpu = 00:05:26 ; elapsed = 00:03:20 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3945 ; free virtual = 11574 Phase 2 Global Placement | Checksum: 17b775e08 Time (s): cpu = 00:05:27 ; elapsed = 00:03:20 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4000 ; free virtual = 11629 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d02c8bb9 Time (s): cpu = 00:05:35 ; elapsed = 00:03:26 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4000 ; free virtual = 11630 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2c100506b Time (s): cpu = 00:05:47 ; elapsed = 00:03:35 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3997 ; free virtual = 11627 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 264c73936 Time (s): cpu = 00:05:49 ; elapsed = 00:03:38 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3989 ; free virtual = 11618 Phase 3.4 Small Shape DP Phase 3.4.1 Small Shape Clustering Phase 3.4.1 Small Shape Clustering | Checksum: 1d58c1e39 Time (s): cpu = 00:06:05 ; elapsed = 00:03:53 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3893 ; free virtual = 11523 Phase 3.4.2 Flow Legalize Slice Clusters Phase 3.4.2 Flow Legalize Slice Clusters | Checksum: 2a3c26bd2 Time (s): cpu = 00:06:08 ; elapsed = 00:03:56 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3901 ; free virtual = 11531 Phase 3.4.3 Slice Area Swap Phase 3.4.3 Slice Area Swap | Checksum: 1f938e028 Time (s): cpu = 00:06:24 ; elapsed = 00:04:37 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3852 ; free virtual = 11481 Phase 3.4 Small Shape DP | Checksum: 1bfb63bab Time (s): cpu = 00:07:02 ; elapsed = 00:04:51 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3878 ; free virtual = 11508 Phase 3.5 Re-assign LUT pins Phase 3.5 Re-assign LUT pins | Checksum: 1b1860d0e Time (s): cpu = 00:07:09 ; elapsed = 00:04:58 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3881 ; free virtual = 11510 Phase 3.6 Pipeline Register Optimization Phase 3.6 Pipeline Register Optimization | Checksum: 1c901052d Time (s): cpu = 00:07:10 ; elapsed = 00:04:59 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3880 ; free virtual = 11510 Phase 3 Detail Placement | Checksum: 1c901052d Time (s): cpu = 00:07:11 ; elapsed = 00:05:00 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3881 ; free virtual = 11510 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 21d1b0e59 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.384 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 175704d4d Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3857 ; free virtual = 11487 INFO: [Place 46-35] Processed net base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST/syncstages_ff[3], inserted BUFG to drive 2791 loads. INFO: [Place 46-35] Processed net base_i/proc_sys_reset_0/U0/peripheral_aresetn[0], inserted BUFG to drive 2305 loads. INFO: [Place 46-45] Replicated bufg driver base_i/proc_sys_reset_0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica INFO: [Place 46-35] Processed net base_i/proc_sys_reset_0/U0/interconnect_aresetn[0], inserted BUFG to drive 2217 loads. INFO: [Place 46-45] Replicated bufg driver base_i/proc_sys_reset_0/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_replica INFO: [Place 46-35] Processed net base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst/syncstages_ff[2][1], inserted BUFG to drive 1968 loads. INFO: [Place 46-35] Processed net base_i/video/hdmi_out/frontend/inst/v_tc/U0/U_VIDEO_CTRL/resetn_out, inserted BUFG to drive 1166 loads. INFO: [Place 46-45] Replicated bufg driver base_i/video/hdmi_out/frontend/inst/v_tc/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.soft_resetn_reg_replica INFO: [Place 46-56] BUFG insertion identified 5 candidate nets. Inserted BUFG: 5, Replicated BUFG Driver: 3, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 18564e77e Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3844 ; free virtual = 11474 Phase 4.1.1.1 BUFG Insertion | Checksum: 16fc67004 Time (s): cpu = 00:08:23 ; elapsed = 00:05:36 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3848 ; free virtual = 11478 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.507. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1d80163e8 Time (s): cpu = 00:08:29 ; elapsed = 00:05:42 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3847 ; free virtual = 11477 Phase 4.1 Post Commit Optimization | Checksum: 1d80163e8 Time (s): cpu = 00:08:30 ; elapsed = 00:05:43 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3847 ; free virtual = 11477 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1d80163e8 Time (s): cpu = 00:08:33 ; elapsed = 00:05:46 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3854 ; free virtual = 11484 Netlist sorting complete. Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.48 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3833 ; free virtual = 11463 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 28124da80 Time (s): cpu = 00:08:42 ; elapsed = 00:05:55 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3834 ; free virtual = 11463 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3834 ; free virtual = 11463 Phase 4.4 Final Placement Cleanup | Checksum: 250d5c6ed Time (s): cpu = 00:08:43 ; elapsed = 00:05:56 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3834 ; free virtual = 11463 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 250d5c6ed Time (s): cpu = 00:08:44 ; elapsed = 00:05:57 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3834 ; free virtual = 11463 Ending Placer Task | Checksum: 1cfa17348 Time (s): cpu = 00:08:44 ; elapsed = 00:05:57 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3833 ; free virtual = 11463 INFO: [Common 17-83] Releasing license: Implementation 274 Infos, 246 Warnings, 9 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:08:57 ; elapsed = 00:06:10 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4059 ; free virtual = 11689 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:08 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3853 ; free virtual = 11646 INFO: [Common 17-1381] The checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:36 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 4002 ; free virtual = 11681 INFO: [runtcl-4] Executing : report_io -file base_wrapper_io_placed.rpt report_io: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.35 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3972 ; free virtual = 11652 INFO: [runtcl-4] Executing : report_utilization -file base_wrapper_utilization_placed.rpt -pb base_wrapper_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file base_wrapper_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.67 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3994 ; free virtual = 11677 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 283 Infos, 246 Warnings, 9 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:19 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3931 ; free virtual = 11616 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:07 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3715 ; free virtual = 11564 INFO: [Common 17-1381] The checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:35 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3858 ; free virtual = 11593 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 4 threads WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST. It has the property IOB=TRUE, but it is not driving or driven by any IO element. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 6 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Checksum: PlaceDB: e5720ab9 ConstDB: 0 ShapeSum: 410bf1f7 RouteDB: a9237698 Phase 1 Build RT Design Nodegraph reading from file. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3672 ; free virtual = 11412 Phase 1 Build RT Design | Checksum: da9011c2 Time (s): cpu = 00:00:26 ; elapsed = 00:00:14 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3606 ; free virtual = 11347 Post Restoration Checksum: NetGraph: cc3f8c09 NumContArr: 7d62442f Constraints: e52aab98 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 22ecc7bd0 Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3647 ; free virtual = 11388 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 22ecc7bd0 Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3608 ; free virtual = 11349 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 22ecc7bd0 Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3608 ; free virtual = 11349 Phase 2.4 Global Clock Net Routing Number of Nodes with overlaps = 0 Phase 2.4 Global Clock Net Routing | Checksum: 1e14d62b6 Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3592 ; free virtual = 11333 Phase 2.5 Update Timing Phase 2.5 Update Timing | Checksum: 22de4513a Time (s): cpu = 00:01:50 ; elapsed = 00:01:01 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3527 ; free virtual = 11267 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.719 | TNS=0.000 | WHS=-0.499 | THS=-82.691| Phase 2.6 Update Timing for Bus Skew Phase 2.6.1 Update Timing Phase 2.6.1 Update Timing | Checksum: 1f306b56d Time (s): cpu = 00:03:08 ; elapsed = 00:01:35 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3511 ; free virtual = 11251 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.719 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.6 Update Timing for Bus Skew | Checksum: 191d20d96 Time (s): cpu = 00:03:08 ; elapsed = 00:01:36 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3515 ; free virtual = 11255 Phase 2 Router Initialization | Checksum: 22acb85df Time (s): cpu = 00:03:09 ; elapsed = 00:01:36 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3515 ; free virtual = 11255 Router Utilization Summary Global Vertical Routing Utilization = 0.00224361 % Global Horizontal Routing Utilization = 0.00155764 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 104605 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 85757 Number of Partially Routed Nets = 18848 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1c7e268c9 Time (s): cpu = 00:03:50 ; elapsed = 00:01:56 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3469 ; free virtual = 11210 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 20230 Number of Nodes with overlaps = 1527 Number of Nodes with overlaps = 145 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.527 | TNS=0.000 | WHS=-0.188 | THS=-0.271 | Phase 4.1 Global Iteration 0 | Checksum: 63be501d Time (s): cpu = 00:07:03 ; elapsed = 00:04:09 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3461 ; free virtual = 11202 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.527 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 105d8733d Time (s): cpu = 00:07:20 ; elapsed = 00:04:22 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3463 ; free virtual = 11204 Phase 4 Rip-up And Reroute | Checksum: 105d8733d Time (s): cpu = 00:07:20 ; elapsed = 00:04:22 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3463 ; free virtual = 11204 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 1321cb8f1 Time (s): cpu = 00:07:51 ; elapsed = 00:04:37 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3457 ; free virtual = 11197 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.527 | TNS=0.000 | WHS=0.011 | THS=0.000 | Phase 5.1 Delay CleanUp | Checksum: 158a40b35 Time (s): cpu = 00:07:52 ; elapsed = 00:04:38 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3458 ; free virtual = 11199 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 158a40b35 Time (s): cpu = 00:07:52 ; elapsed = 00:04:38 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3458 ; free virtual = 11199 Phase 5 Delay and Skew Optimization | Checksum: 158a40b35 Time (s): cpu = 00:07:52 ; elapsed = 00:04:38 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3458 ; free virtual = 11199 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1c67307ae Time (s): cpu = 00:08:15 ; elapsed = 00:04:49 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3462 ; free virtual = 11203 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.527 | TNS=0.000 | WHS=0.011 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 210b94248 Time (s): cpu = 00:08:16 ; elapsed = 00:04:50 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3462 ; free virtual = 11202 Phase 6 Post Hold Fix | Checksum: 210b94248 Time (s): cpu = 00:08:16 ; elapsed = 00:04:50 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3462 ; free virtual = 11202 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 6.15494 % Global Horizontal Routing Utilization = 6.4549 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 172a9528c Time (s): cpu = 00:08:18 ; elapsed = 00:04:51 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3458 ; free virtual = 11198 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 172a9528c Time (s): cpu = 00:08:18 ; elapsed = 00:04:52 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3460 ; free virtual = 11201 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 172a9528c Time (s): cpu = 00:08:27 ; elapsed = 00:05:00 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3467 ; free virtual = 11208 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.527 | TNS=0.000 | WHS=0.011 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 172a9528c Time (s): cpu = 00:08:28 ; elapsed = 00:05:01 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3474 ; free virtual = 11215 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:08:28 ; elapsed = 00:05:01 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3558 ; free virtual = 11299 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 300 Infos, 252 Warnings, 9 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:08:49 ; elapsed = 00:05:16 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3558 ; free virtual = 11299 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:19 ; elapsed = 00:00:09 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3304 ; free virtual = 11251 INFO: [Common 17-1381] The checkpoint '/home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:38 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3487 ; free virtual = 11288 INFO: [runtcl-4] Executing : report_drc -file base_wrapper_drc_routed.rpt -pb base_wrapper_drc_routed.pb -rpx base_wrapper_drc_routed.rpx Command: report_drc -file base_wrapper_drc_routed.rpt -pb base_wrapper_drc_routed.pb -rpx base_wrapper_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:41 ; elapsed = 00:00:20 . Memory (MB): peak = 5918.520 ; gain = 0.000 ; free physical = 3423 ; free virtual = 11225 INFO: [runtcl-4] Executing : report_methodology -file base_wrapper_methodology_drc_routed.rpt -pb base_wrapper_methodology_drc_routed.pb -rpx base_wrapper_methodology_drc_routed.rpx Command: report_methodology -file base_wrapper_methodology_drc_routed.rpt -pb base_wrapper_methodology_drc_routed.pb -rpx base_wrapper_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 4 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/hughesyang/Downloads/PYNQ-master/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:01:35 ; elapsed = 00:00:41 . Memory (MB): peak = 6234.758 ; gain = 316.238 ; free physical = 3657 ; free virtual = 11461 INFO: [runtcl-4] Executing : report_power -file base_wrapper_power_routed.rpt -pb base_wrapper_power_summary_routed.pb -rpx base_wrapper_power_routed.rpx Command: report_power -file base_wrapper_power_routed.rpt -pb base_wrapper_power_summary_routed.pb -rpx base_wrapper_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 313 Infos, 253 Warnings, 9 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:01:00 ; elapsed = 00:00:38 . Memory (MB): peak = 6258.766 ; gain = 24.008 ; free physical = 3503 ; free virtual = 11322 INFO: [runtcl-4] Executing : report_route_status -file base_wrapper_route_status.rpt -pb base_wrapper_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file base_wrapper_timing_summary_routed.rpt -pb base_wrapper_timing_summary_routed.pb -rpx base_wrapper_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. report_timing_summary: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 6258.766 ; gain = 0.000 ; free physical = 3448 ; free virtual = 11281 INFO: [runtcl-4] Executing : report_incremental_reuse -file base_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file base_wrapper_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 6258.766 ; gain = 0.000 ; free physical = 3436 ; free virtual = 11271 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file base_wrapper_bus_skew_routed.rpt -pb base_wrapper_bus_skew_routed.pb -rpx base_wrapper_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. INFO: [Memdata 28-167] Found XPM memory block base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. Command: write_bitstream -force base_wrapper.bit Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' INFO: [Common 17-83] Releasing license: Implementation 361 Infos, 254 Warnings, 9 Critical Warnings and 1 Errors encountered. write_bitstream failed ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst () base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst () If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. INFO: [Common 17-206] Exiting Vivado at Thu Dec 10 00:22:23 2020... [Thu Dec 10 00:22:24 2020] impl_1 finished WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1' wait_on_run: Time (s): cpu = 02:34:48 ; elapsed = 02:01:20 . Memory (MB): peak = 10359.676 ; gain = 0.000 ; free physical = 3464 ; free virtual = 11300 # write_hw_platform -include_bit -force ./${overlay_name}.xsa INFO: [Vivado 12-4895] Creating Hardware Platform: ./base.xsa ... INFO: [Hsi 55-2053] elapsed time for repository (/home/hughesyang/tools/Vivado/2020.1/data/embeddedsw) loading 1 seconds INFO: [Project 1-1042] Successfully generated hpfm file write_project_tcl: Time (s): cpu = 00:07:53 ; elapsed = 00:06:52 . Memory (MB): peak = 10359.676 ; gain = 0.000 ; free physical = 7289 ; free virtual = 15470 ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform.. update_compile_order -fileset sources_1