Summary

IP core name	untitled_ip
IP core version	1.0
IP core folder	C:\Users\sumanmondal\Desktop\ZZ_intern\example_testing\test\ipcore\untitled_ip_v1_0
IP core zip file name	untitled_ip_v1_0.zip
Target platform	Generic Xilinx Platform
Target tool	Xilinx Vivado
Target language	VHDL
Model	untitled
Model version	1.0
HDL Coder version	3.13
IP core generated on	08-Mar-2021 16:59:17
IP core generated for	Subsystem

Target Interface Configuration

You chose the following target interface configuration for untitled :

Processor/FPGA synchronization mode: Free running

Target platform interface table:

Port Name	Port Type	Data Type	Target Platform Interfaces	Bit Range / Address / FPGA Pin
In1	Inport	ufix16_En15	AXI4-Lite	x"100"
In2	Inport	ufix16_En15	AXI4-Lite	x"104"
Out1	Outport	ufix16_En14	AXI4-Lite	x"108"

Register Address Mapping

The following AXI4-Lite bus accessible registers were generated for this IP core:

Register Name	Address Offset	Description
IPCore_Reset	0x0	write 0x1 to bit 0 to reset IP core
IPCore_Enable	0x4	enabled (by default) when bit 0 is 0x1
IPCore_Timestamp	0x8	contains unique IP timestamp (yymmddHHMM): 2103081659
In1_Data	0x100	data register for Inport In1
In2_Data	0x104	data register for Inport In2
Out1_Data	0x108	data register for Outport Out1

The AXI4 slave write register readback is OFF for the IP core.
The register address mapping is also in the following C header file for you to use when programming the processor:
include\untitled_ip_addr.h
The IP core name is appended to the register names to avoid name conflicts.

IP Core User Guide

Theory of Operation

This IP core is designed to be connected to an embedded processor with an AXI4-Lite interface. The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite interface, the processor can control the IP core, and read and write data from and to the IP core.

For example, to reset the IP core, write 0x1 to the bit 0 of IPCore_Reset register. To enable or disable the IP core, write 0x1 or 0x0 to the IPCore_Enable register. To access the data ports of the MATLAB/Simulink algorithm, read or write to the associated data registers.



Processor/FPGA Synchronization

The Free running mode means there is no explicit synchronization between embedded processor software execution (SW) and the IP core (HW). SW and HW runs independently. The data written from the processor to IP core takes effect immediately, and the data read from the IP core is the latest data available on the IP core output ports.



Xilinx Vivado Environment Integration

This IP Core is generated for the Xilinx Vivado environment. The following steps are an example showing how to integrate the generated IP core into Xilinx Vivado environment:

1. The generated IP core is a zip package file under the IP core folder. Please check the Summary section of this report for the IP zip file name and folder.
2. In the Vivado project, go to Project Settings -> IP -> Repository Manager, add the folder containing the IP zip file as IP Repository.
3. In Repository Manger, click the "Add IP" button to add IP zip file to the IP repository. This step adds the generated IP into the Vivado IP Catalog.
4. In the Vivado project, find the generated IP core in the IP Catalog under category "HDL Coder Generated IP". In you have a Vivado block design open, you can add the generated IP into your block design.
5. Connect the AXI4_Lite port of the IP core to the embedded processor's AXI master port.
6. Connect the clock and reset ports of the IP core to the global clock and reset signals.
7. Assign an Offset Address for the IP core in the Address Editor.
8. Connect external ports and add FPGA pin assignment constraints to constraint file.
9. Generate FPGA bitstream and download the bitstream to target device.

If you are targeting Xilinx Zynq hardwares supported by HDL Coder Support Package for Xilinx Zynq Platform, you can select the board you are using in the Target platform option in the Set Target > Set Target Device and Synthesis Tool task. You can then use Embedded System Integration tasks in HDL Workflow Advisor to help you integrate the generated IP core into Xilinx Vivado environment.

IP Core File List

The IP core folder is located at:
C:\Users\sumanmondal\Desktop\ZZ_intern\example_testing\test\ipcore\untitled_ip_v1_0
Following files are generated under this folder:

IP core zip file
untitled_ip_v1_0.zip

IP core report
doc\untitled_ip_core_report.html

IP core HDL source files
hdl\vhdl\untitled_ip_src_Subsystem.vhd
hdl\vhdl\untitled_ip_dut.vhd
hdl\vhdl\untitled_ip_axi_lite_module.vhd
hdl\vhdl\untitled_ip_addr_decoder.vhd
hdl\vhdl\untitled_ip_axi_lite.vhd
hdl\vhdl\untitled_ip.vhd

IP core C header file
include\untitled_ip_addr.h