Accessing BRAM from HLS IP

[cathalmccabe]

By making the a[50] an axilite, means you need to write all the values of a to the IP via AXI lite.
I would suggest you do it like this:

Tutorial: AXI Master interfaces with HLS IP

PYNQ HLS AXI Master tutorial Introduction Previous tutorials show how to build IP with AXI stream interfaces and how they can be connected in a Vivado project to an AXI DMA. The DMA can be controlled from PYNQ to send data to the IP and receive results. AXI stream interfaces are useful if you are connecting multiple IP together in a dataflow type architecture. However, you don’t have to use AXI streams and DMAs with HLS IP. HLS supports AXI master interfaces which can read and write data as r…

Allow HLS to read and write from an external interface. In this example the AXI master is connected to PS DRAM.
You can initialize the PS DRAM from software, and pass the address to the HLS IP.

If you really want to do it as you described, you could connect the AXI Master of the HLS IP to one port of a dual port BRAM, and connect the other port of the BRAM to the PS. This would be slower than the first method in most cases, and limits the available memory the HLS IP can access.

Cathal