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About the Learn category
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0
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463
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February 16, 2019
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GPS on PYNQ
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0
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10
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July 5, 2022
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Are PYNQ concept worth to move onto general FPGA with softcore CPU apart from SOC-based FPGA?
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0
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14
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July 4, 2022
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ZYNQ Ultrascale+ FIR DMA
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0
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27
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July 1, 2022
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Readability in Python and Java
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3
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28
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June 30, 2022
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Tutorial: PYNQ DMA (Part 1: Hardware design)
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10
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4081
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June 27, 2022
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Testing Tensorflow 2.5 in Zybo-Z7 running Pynq 2.7
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6
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192
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June 15, 2022
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Pynq 2.7 for Zybo-Z7
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7
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346
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June 15, 2022
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Creating A DPU-Compatible Platform For PYNQ
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3
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66
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June 10, 2022
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MNIST + AXI Stream on PYNQ 2.7 (Attention to Details)
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2
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138
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June 6, 2022
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Changing the IP in the Composable Pipeline
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2
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40
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June 3, 2022
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Servo motor on PYNQ
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0
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49
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May 24, 2022
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Using PyPI to deliver FPGA Overlays
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1
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1425
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March 15, 2022
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Testing PyTorch 1.8 in Zybo-Z7 running Pynq 2.7
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0
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101
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May 10, 2022
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Pynq - Z2 Pmod
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2
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60
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May 6, 2022
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Kubernetes for AMD-Xilinx Platforms
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0
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336
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May 2, 2022
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Bluetooth on FPGA with ESP32
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0
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62
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April 26, 2022
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Tutorial: AXI Master interfaces with HLS IP
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3
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347
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April 20, 2022
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Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.6)
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10
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3881
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April 14, 2022
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FPGA as USB Device
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0
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113
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April 12, 2022
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Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ)
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4
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2130
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April 1, 2022
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Double tap with accelerometer
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0
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79
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March 1, 2022
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Interactive C++ on the Kria-SoM in Jupyter Lab
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2
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759
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February 21, 2022
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Build PYNQ-2.4 SD card Image for Zedboard v2018.3
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1
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1538
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February 17, 2022
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Tutorial PYNQ: microblaze
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0
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190
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February 1, 2022
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Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)
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1
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2073
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February 4, 2022
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Pynq 2.6 custom board image build method that works
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4
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1222
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January 21, 2022
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100 Gigabit Ethernet for RFSoC-PYNQ Overlays
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3
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1707
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January 5, 2022
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Cloning a git repository into your board connected to computer
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1
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290
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December 13, 2021
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Developing Verilog AXI Stream Overlays and interfacing to ZYNQ
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13
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2277
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December 7, 2021
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