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About the Learn category
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0
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879
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February 16, 2019
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Tutorial: PYNQ DMA (Part 1: Hardware design)
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31
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31191
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March 7, 2025
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PYNQ-Z1 pinout
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2
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172
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March 4, 2025
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ADC input on Pynq-ZU
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1
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15
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February 24, 2025
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Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) [Part 1]
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10
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499
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February 14, 2025
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PYNQ Coverage
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2
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42
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January 23, 2025
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Auxiliary materials
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0
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16
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January 5, 2025
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Tutorial: using a HLS stream IP with DMA (Part 3: Using the HLS IP from PYNQ)
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4
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7832
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January 3, 2025
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Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.6)
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12
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11258
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December 31, 2024
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Tutorial: Creating a hardware design for PYNQ
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11
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33313
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December 7, 2024
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PYNQ-ZU labs
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1
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45
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November 25, 2024
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100 Gigabit Ethernet for RFSoC-PYNQ Overlays
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8
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6479
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November 25, 2024
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Working code example for GPIO ZYNQ7000
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0
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27
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November 21, 2024
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About PYNQ support for Arty-Z7 board
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3
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29
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September 30, 2024
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Debugging Common DMA Issues [Part 3]
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9
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668
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September 3, 2024
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Tutorial: Using a new hardware design with PYNQ (AXI GPIO)
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1
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12871
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August 20, 2024
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PYNQ 2.7 DFX Partial Reconfiguration under Vivado 2020.2 - TCL Script ALL-IN-ONE
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6
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700
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August 8, 2024
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ZCU216 basic ADC and DAC IQ send and receive example
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0
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54
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July 31, 2024
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Testing Tensorflow 2.5 in Zybo-Z7 running Pynq 2.7
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10
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2525
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July 25, 2024
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Testing PyTorch 1.8 in Zybo-Z7 running Pynq 2.7
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1
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1551
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July 25, 2024
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Pynq 2.7 for Zybo-Z7
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16
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5316
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July 25, 2024
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Using an ILA without Physical micro USB cable [Part 4]
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2
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259
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June 17, 2024
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Connecting to the ILA using HW Server [Part 2]
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2
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317
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June 17, 2024
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Changing the IP in the Composable Pipeline
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19
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1215
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June 3, 2024
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Tutorial: AXI Master interfaces with HLS IP
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7
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10161
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April 29, 2024
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Seeking Guidance on Learning ADC and DAC in RFSoC 4x2
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6
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426
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April 19, 2024
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PYNQ 3.0.1 for Zybo Z7-20
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2
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880
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April 5, 2024
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PYNQ 2.7 DFX Partial Reconfiguration under Vivado 2020.2
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8
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2101
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April 3, 2024
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Tutorial: using a HLS stream IP with DMA (Part 2: Vivado design)
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4
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8330
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September 27, 2023
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Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)
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2
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15802
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March 22, 2024
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