|
About the Learn category
|
|
0
|
943
|
February 16, 2019
|
|
End-to-End Machine Learning Hardware Acceleration on the AMD AUP-ZU3 SoC/FPGA
|
|
0
|
34
|
June 9, 2026
|
|
Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.3)
|
|
13
|
9439
|
May 26, 2026
|
|
RFSoC 4x2 Bare-Metal Tutorial: 10 MHz DAC–ADC Loopback
|
|
1
|
168
|
April 29, 2026
|
|
Tutorial: AXI Master interfaces with HLS IP
|
|
6
|
12491
|
February 24, 2026
|
|
Building a demo kernel module for PYNQ v3.1
|
|
1
|
70
|
January 8, 2026
|
|
Tutorial: Creating a hardware design for PYNQ
|
|
18
|
38853
|
December 21, 2025
|
|
PYNQ and QICK relations
|
|
0
|
81
|
November 1, 2025
|
|
Vitis IDE examples or similar for rfsoc4x2
|
|
0
|
67
|
October 17, 2025
|
|
Which Ebook Is Best for Python?
|
|
5
|
992
|
October 12, 2025
|
|
Tutorial: PYNQ DMA (Part 1: Hardware design)
|
|
30
|
41173
|
October 11, 2025
|
|
Debugging Common DMA Issues [Part 3]
|
|
7
|
2051
|
September 3, 2024
|
|
Matching tile DAC ADC on VIVADO to actual location on RFSoc4x2 board
|
|
1
|
98
|
July 31, 2025
|
|
Overlay with DAC ADC in rfsock4x2
|
|
13
|
426
|
July 31, 2025
|
|
DDR setting for my rfsoc4x2 proccesor
|
|
5
|
185
|
July 17, 2025
|
|
Understanding the interconnect logic of given base overlay
|
|
2
|
96
|
July 7, 2025
|
|
Use of the arduino pins in PYNQ-Z2
|
|
0
|
103
|
June 16, 2025
|
|
Building a Kernel Module for a ZYNQ PL peripheral
|
|
0
|
123
|
June 15, 2025
|
|
Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.6)
|
|
11
|
12685
|
June 6, 2025
|
|
Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ)
|
|
4
|
21067
|
January 10, 2023
|
|
Seeking Guidance on Learning ADC and DAC in RFSoC 4x2
|
|
7
|
948
|
May 12, 2025
|
|
Tutorial: Using a new hardware design with PYNQ (AXI GPIO)
|
|
5
|
14322
|
April 17, 2025
|
|
Connecting to the ILA using HW Server [Part 2]
|
|
2
|
1228
|
April 2, 2025
|
|
Install ROS Noetic on PYNQ image
|
|
2
|
682
|
March 27, 2025
|
|
PYNQ-Z1 pinout
|
|
2
|
1002
|
March 4, 2025
|
|
ADC input on Pynq-ZU
|
|
1
|
121
|
February 24, 2025
|
|
Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) [Part 1]
|
|
7
|
1693
|
February 14, 2025
|
|
PYNQ Coverage
|
|
2
|
106
|
January 23, 2025
|
|
Auxiliary materials
|
|
0
|
45
|
January 5, 2025
|
|
Tutorial: using a HLS stream IP with DMA (Part 3: Using the HLS IP from PYNQ)
|
|
4
|
9244
|
January 3, 2025
|
