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About the Learn category
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0
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514
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February 16, 2019
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100 Gigabit Ethernet for RFSoC-PYNQ Overlays
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4
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2193
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October 4, 2022
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PYNQ 2.7 DFX Partial Reconfiguration under Vivado 2020.2
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0
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41
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September 29, 2022
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USB3320 not able to detect the devicec connected
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5
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48
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September 26, 2022
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Tutorial: PYNQ DMA (Part 1: Hardware design)
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26
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5828
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September 19, 2022
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Tutorial: using a HLS stream IP with DMA (Part 3: Using the HLS IP from PYNQ)
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1
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1608
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August 27, 2022
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Tutorial: Creating a new Verilog Module Overlay
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2
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2491
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August 25, 2022
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Docker, Xilinx Platforms & PYNQ
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6
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2476
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August 25, 2022
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Pynq 2.7 for Zybo-Z7
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11
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996
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August 12, 2022
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Starting PYNQ Programs At Boot
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7
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2357
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August 10, 2022
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Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ)
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5
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3086
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August 5, 2022
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GPS on PYNQ
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0
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46
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July 5, 2022
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Are PYNQ concept worth to move onto general FPGA with softcore CPU apart from SOC-based FPGA?
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0
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70
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July 4, 2022
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ZYNQ Ultrascale+ FIR DMA
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0
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82
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July 1, 2022
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Readability in Python and Java
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3
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77
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June 30, 2022
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Testing Tensorflow 2.5 in Zybo-Z7 running Pynq 2.7
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6
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373
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June 15, 2022
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Creating A DPU-Compatible Platform For PYNQ
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3
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114
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June 10, 2022
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MNIST + AXI Stream on PYNQ 2.7 (Attention to Details)
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2
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364
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June 6, 2022
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Changing the IP in the Composable Pipeline
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2
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82
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June 3, 2022
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Servo motor on PYNQ
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0
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84
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May 24, 2022
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Using PyPI to deliver FPGA Overlays
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1
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1531
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March 15, 2022
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Testing PyTorch 1.8 in Zybo-Z7 running Pynq 2.7
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0
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257
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May 10, 2022
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Pynq - Z2 Pmod
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2
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106
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May 6, 2022
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Kubernetes for AMD-Xilinx Platforms
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0
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520
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May 2, 2022
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Bluetooth on FPGA with ESP32
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0
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126
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April 26, 2022
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Tutorial: AXI Master interfaces with HLS IP
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3
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827
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April 20, 2022
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Tutorial: Rebuilding the PYNQ base overlay (PYNQ v2.6)
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10
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4620
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April 14, 2022
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FPGA as USB Device
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0
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174
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April 12, 2022
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Double tap with accelerometer
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0
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113
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March 1, 2022
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Interactive C++ on the Kria-SoM in Jupyter Lab
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2
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982
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February 21, 2022
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