Hi David,
If you are accessing the DRAM through the HP ports, you are correct, these HP ports are 64 bits wide.
HLS can generate IP interfaces that are varying sizes, including 512 bit. To connect a 512 bit interface from your IP to the HP port, you need an adapter that will convert between the two interfaces. See “AXI Interconnect” or “AXI Smartconnect” IP in Vivado)
Your 512 bit interfaces in the adapter will be broken down into 8 blocks of 64 bits each, and the adapter will manage the transfer of data over a number of clock cycles.
You can run your IP, and the HP ports at different clock speeds. You can specify different clocks for each side of the adapter. However, it is probably unlikely that you want to build a design like this with a ratio of 512:64 , as you probably won’t be running your IP 8x slower than the max speed of the HP ports. It is much more likely you would use say a 128 bit interfaces, so you only have a 2x step up or down.
The 512 bit interface on your IP will also consume more FPGA resources than a smaller width interface.
Unless you can benefit from a wider width, you will be better using a 64-bit width for your HLS IP.
For info, if you have internal interfaces between IP in your design, you may choose to use wider interfaces for these.
One nice thing about HLS and how the design is connected in Vivado is that it is relatively easy to try different configurations. The adapter should automatically manage the different port sizes.
Cathal