Hi, I want to achieve axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2. I meet some problem and feel confusing when using register map.
- axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2
- know more about FPGA and axi
Vivado 2019.1 Vivado HLS 2019.1 vs Vivado 2021.2, Vitis HLS 2021.2
Operations with Vivado (HLS) 2019.1:
Step on blog axi4.
HW IP works well in AXI Burst works well on Pynq Z1/Z2 with Vivado HLS:
Operations with Vitis HLS and Vivado2021.2:
Step on blog axi4 again.
- Unlike in version 2019.1, there is double in and out in version 2021.2.
- HW IP seems not work in my operations。
I checked the AXI4 Master Interface, it will take me some time to figure it out.
At the same time, may I ask if there would be a right way to use HW IP on Pynq.
Here is the interface:
#pragma HLS INTERFACE s_axilite port=return bundle=sqrt
#pragma HLS INTERFACE s_axilite port=len bundle=sqrt
#pragma HLS INTERFACE m_axi depth=100 port=out offset=slave bundle=output
#pragma HLS INTERFACE m_axi depth=100 port=in offset=slave bundle=input
#pragma HLS INTERFACE s_axilite port=in bundle=sqrt
#pragma HLS INTERFACE s_axilite port=out bundle=sqrt