RegisterMap for m_axi HLS IP and a HLS version comparison case

Support
1

Hi, I want to achieve axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2. I meet some problem and feel confusing when using register map.

Target:

  1. axi burst on pynq-Z1/Z2 with Vitis HLS 2021.2
  2. know more about FPGA and axi

Environment:
Pynq-Z1
Vivado 2019.1 Vivado HLS 2019.1 vs Vivado 2021.2, Vitis HLS 2021.2

Operations with Vivado (HLS) 2019.1:
Step on blog axi4.
Result:
HW IP works well in AXI Burst works well on Pynq Z1/Z2 with Vivado HLS:

image
image779×619 8.41 KB

Operations with Vitis HLS and Vivado2021.2:
Step on blog axi4 again.
Result:

  1. Unlike in version 2019.1, there is double in and out in version 2021.2.
  2. HW IP seems not work in my operations。
    image
    image561×679 13.9 KB

I checked the AXI4 Master Interface, it will take me some time to figure it out.
At the same time, may I ask if there would be a right way to use HW IP on Pynq.

Here is the interface:

#pragma HLS INTERFACE s_axilite port=return bundle=sqrt
#pragma HLS INTERFACE s_axilite port=len bundle=sqrt
#pragma HLS INTERFACE m_axi depth=100 port=out offset=slave bundle=output
#pragma HLS INTERFACE m_axi depth=100 port=in offset=slave bundle=input
#pragma HLS INTERFACE s_axilite port=in bundle=sqrt
#pragma HLS INTERFACE s_axilite port=out bundle=sqrt
2

The default settings and behaviour of HLS can change over the different versions.

The number of registers generated depends on the size of the data. If you have a 32 bit value, you will only have one register. 64 bit = 2 registers. You will also see this difference if you move from a Zynq 7000 (32-bit) design to a Zynq Ultrascale+ (64 bit) or if you set the size of your data bus to these widths in different designs.

Cathal