AXI FULL transfer time

[cathalmccabe]

The Python code is running on the CPU, on an OS. There will be some overhead with any Python call, and there will be some variability.

If you are using the AXI GP port, these are not AXI full, so bursts are not being used and these are individual transactions. the Python calls will be dominating the AXI transfers.

You can use the AXI HP ports for “AXI FULL” interfaces. The PL can “pull” the data from PS in this case, rather than the PS “pushing” data opver AXI GP. DMA is one way to do this, but it needs some Python calls to setup, and again this overhead will likley dominate transfer of 24 values. You could build an IP with an AXI full interface that can initiate its own transactions. This would give highest performance.

If you search forums, there has been some discussion on this by others. One thread:

MMIO write is too slow

It might be interesting for others if you could post the transfer time, and if this is good enough for your application. (I would be interested ) 16 bits instead of 32 bits is effectively halving your bandwidth/doubling the transfer time although you need to balance this against the time taken to pack your data in software. There are python packages to do this efficiently than writing your own python code to do this. As Peter mentioned, this is a quick fix. You can improve the data tran…

Cathal