PYNQ: PYTHON PRODUCTIVITY

I wonder if I am using the speed of dram and DMA to the maximum

hello, I just check the speed of data transfer between ps and pl.

I use AXI-Stream interface with DMA Module.

I made a simple module that takes data from the dram and stores it back in the dram.

And I check transfer speed with various burst width and TDATA width.

This is my result.

I use pynq-z2 board and, I give 525Mhz to DDR in ps’ clock configuration option.

Also, I give 100Mhz to axi DMA module.

Is there a way to send and receive data faster than the current speed?

Thank you.

@Jongmin_Park,

The High Performance (HP) interfaces in the Zynq device supports 32 and 64 bit data width. To maximize performance, you should select 64-bit. With that in mind, the maximum theoretical performance you can get will depend on the clock frequency in the PL side. max performance = data_width * clock_frequency

In your particular case 64-bit * 100 MHz = 6.4 Gbit/s (800 MB/s).

Is there a way to send and receive data faster than the current speed?

Increase the PL clock frequency.

Mario

2 Likes

Thank you for your kind reply!