AXI INTC output ( Level or edge) for PYNQ

Support
1

Hi,
Quick Question -
Does it matter if AXI INTC interrupt output to processor from PL is configured as Edge or level interrupt ?
for PYNQ setup to work .

BR

2

It should be level triggered, active high as that is what we configure the ARM interrupt controller to expect.

Peter

3

Hi Peter ,

First of all, sorry to awaken this thread with this question…

Could you provide me any link that clarifies the choice of level-triggered interrupts (instead of edge-triggered) in the PYNQ framework? Why is the ARM interrupt controller not configure with edge-triggered interrupts?
I am probably missing some knowledge here and would like to read up on this…

Thank you!

Kind regards,
Yuri

4

Hi @Yuri_Cauwerts
one reason that I know is that the CPU needs to have enough time to detect the interrupt pulse. specially if the clocks are different, this is possible that the edge is not detected by the ARM core. the edges of different clocks are not synchronize and doesn’t not happen at the same exact moment.
I have this experience in RFSoC: the PL part was generating a pulse, but the clock of PL was multiple times faster than the ARM cores. Then the CPU wasn’t able to detect it. I need to make a pulse with larger length, then the CPU detects it.

Hope it could help.
Kind Regards,
Mo

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