Hi, thanks again for the info. I just found out that the FPGA manager can be disabled in PYNQ 2.5.4 as well: For v2.5 is there a way to have it load a bitstream during power-up like it did in prior versions of PYNQ? - Support - PYNQ. Since my design is in Vivado 2019.1 I might stick to it.
So… I read the overlays section and now I’m a bit confused. Let’s say that I have a base design. Now, I design two different overlays. One with LED control IP, and a second with Button sense IP. Just to clarify: at any given moment only ONE of overlays (LED)/(Button) can be loaded?
The way I now understand it then is: if I wanted to use the buttons to control the LEDs I’d need to either write a single overlay with both IPs or perform (rather slow) online bitstream runtime reconfiguration. Correct? The manual is a bit obscure about this point.