Pynq version: 2.6
Board: Custom, Z020
I am trying to get Pynq to work with an HDL only based image, no block diagram. In Pynq 2.3 I was able to create a basic block diagram and slip in my own BIT file (BIT did not match the BD) and everything worked great. I had access to both AXI Master IFs, could toggle MIO/EMIO, etc.
I’ve recently moved to Pynq 2.6, created some test overlays and was ready to load my BIT file but every time the system crashes after loading the overlay in Jupyter Notebooks, kind of like what happens when you write to an undefined GP AXI address.
In my dummy BD/HWH files (since .tcl, .hwh, .bit files must be present) I have a really basic setup with an interrupt controller and 2 AXI crossbars with some BRAM controllers. This works by itself with the matching BIT file, however, when I slip my custom BIT file into the system the image gets configured but my Pynq drops all ethernet connections (FPGA logic continues to run).
This brought me here…is there a block diagram agnostic method for running Pynq 2.6?
Is there a work around that allows the Pynq framework to access all of the Zynq peripherals: GP AXI, ACP port, HP AXI, irq_f2p(0:0), MIO, EMIO, etc?
My next step for tomorrow is checking to see if the GP AXI bus is being accessed after configuring the FPGA without being told to do so, just to check it off of my list.