Debugging Common DMA Issues [Part 3]

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Thanks for these tutorials, Mario.

I’m an undergraduate student researcher that is temporarily covering for a grad student on an RFSoC 4x2 project. Both the grad student and myself are running into issues with DMA, and I’m aware that Part 3 of these tutorials cover troubleshooting. I’m trying to backtrack to a known-working design, so I modified the 1_0_mpsoc_dma_overlay.tcl script to work with the RFSoC 4x2 board, and I’ve been able to get through this tutorial successfully.

After completing Part 1, I started experimenting with the notebook’s commands in order to help develop my understanding of how DMA works so that I can understand why my existing design is failing. In doing so, I’ve developed the following questions:

  1. In your notebook, if I check the idle status of dma_send or dma_recv immediately after the following block of code, both return “False”. However, both will return “True” after a transfer has been completed. This prevents me from setting up a reliable if/else that checks idle status before initiating a transfer. Is there something wrong with my implementation of your script or is this expected?
    from pynq import Overlay, allocate, PL
    import numpy as np
    PL.reset()
    ol = Overlay('dma_wrapper.bit')
    dma = ol.axi_dma
    dma_send = ol.axi_dma.sendchannel
    dma_recv = ol.axi_dma.recvchannel

  2. I’ve found that I can run the following block repeatedly without issue.
    dma_send.transfer(input_buffer)
    dma_recv.transfer(output_buffer)
    dma_send.wait()
    dma_recv.wait()
    However, if I change this block to the following code, the cell will hang during its seventh execution and require kernel interruption.
    dma_send.transfer(input_buffer)
    dma_send.wait()
    After that kernel interruption, I can then run the following code repeatedly, which will hang on its eighth execution.
    dma_recv.transfer(output_buffer)
    dma_recv.wait()
    Is this behavior expected or is there an issue with my adaptation of your block design. If this is normal, could you please help me understand why this is occurring?

Thanks in advance for any time anyone might spend addressing my questions.

  • Shawn Feezer