I have written my kernel code in Vivado HLS and validated it using C/RTL Cosimulation. I exported the IP and created the block design and validated it in Vivado. I generated the bitstream for the validated block design. I also verified it on the PYNQ-Z2 board.
When I measured the execution time using the “time” python package in the host program, I noticed a discrepancy in the execution time on the PYNQ board and the time I calculated after the C/RTL Cosim. I calculated the execution time of the kernal after C/RTL cosim as follow:
Execution time = Latency x Clock Period
The timing on the board was calculated as follows:
start = time.time()
while pg_ip.read(0x01 & 0x4)!= 0x04:
end = time.time()
pg_ip.write(0x00,0x00) # stop
These two timings do not match.
What is the reason for having different times?