How to get an object which identifies the HW design running in PL loaded during the boot-up phase?

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1

  • PYNQ Version: 2.3 (Because I’m using Vivado 2018_R2 and other SW based on it)

  • Using a customized image.

  • Board(s): Zed evaluation board + FMCOMMS2

  • Detailed problem:

  • I’m able to load my own bitstream into PL and work with it in a Python script with PYNQ support on a PYNQ-Z1 board and a Zed evaluation board.

  • I’m able to create a PYNQ-supported image for Zed evaluation board (which has one FMCOMMS2 attached to it).

  • I’m able to create an image by Petalinux with the tools/settings from ADI web site to have FMCOMMS2 being detected and work on Zed evaluation board. In this case, a bitstream generated from ADI HDL is combined into BOOT.BIN and is loaded during boot-up phase.

  • Then, we have one combined image – “BOOT.BIN/image.ub with PYNQ support and ad9361 support and bitstream from ADI HDL” + “PYNQ file system”.

  • Now I’m going to add my own IP (a small design) into that default bitstream from ADI HDL, so I can work with my own IP design in a PYNQ Python script and send data to FMCOMMS2 (ad9361) for transmitting data at the same time (in the same PYNQ Python script).

  • But, in that case, it looks like I will not need use “overlay()” to load bitstream again because that bitstream is supposed to have been loaded and working during the boot-up phase. (Maybe I can load the same bitstream again by “overlay()” in my PYNQ Python script but not sure what will happen for other functions which have been working.)

  • Thus I’m thinking if I can get an object in a PYNQ Python script which identifies the current working HW design in PL (from the bitstream which has been loaded during boot-up phase) w/o loading the bitstream by “overlay()”, and thus I can use it for my following actions in my PYNQ Python script. Would you please advise me how to do it? Or maybe I misunderstand something here. Thx a lot for the advice!

  • Error messages: N/A

  • Steps to reproduce the problem: N/A

  • Detailed steps you have tried to resolve the problem: Checked PYNQ docs but couldn’t find a clear answer about it or maybe I was missing or misunderstood something in the PYNQ docs.

1 Like
2

You can use

overlay_handle = overlay("yourdesign.bit", download = false)

This will give you a Python reference to the Overlay, but doesn’t download the bitstream. Is this what you need?

Incidentally, if you did want to download the Overlay later, you can run
overlay_handle.download()

Reference:
https://pynq.readthedocs.io/en/v2.3/pynq_package/pynq.overlay.html#pynq.overlay.Overlay

Cathal

1 Like
3

Hi Cathal,

Thanks a lot for your advice!

The default bitstream file “system_top.bit” is from ADI HDL project for Zed board + FMCOMMS.
We then added our own IP xxx_0 and two DMA components for it, axi_dma_0 and axi_dma_1, into that default HW design “system_top”.
The new generated “system_top.bit” includes our own IP and those 2 additional DMA components now.

After the device (Zed+FMCOMMS) boots up, that bitstream “system_top.bit” is supposed to have been loaded during the boot-up phase.
From kernel debug message and iio_info, it looks like it’s working and FMCOMMS can be detected.

dmesg:
[ 1.363446] ad9361 spi0.0: ad9361_probe : enter (ad9361)
[ 1.606620] ad9361 spi0.0: ad9361_probe : AD936x Rev 2 successfully initialized
[ 1.647615] cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x79024000 mapped to 0xe08aa000, probed DDS AD9361
[ 2.736498] cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.00.b) at 0x79020000 mapped to 0xe0988000, probed ADC AD9361 as MASTER

iio_info:
iio:device1: ad9361-phy

And then I followed the advice in a PYNQ Python script listed below to try to access the components we added.

from pynq import Overlay
import numpy as np
from pynq import Xlnk
from pynq.lib import dma
from scipy.linalg import dft
import matplotlib.pyplot as plt
from pynq import MMIO

ol=Overlay('system_top.bit', download = False)

dma1=ol.axi_dma_0
dma2=ol.axi_dma_1
...

But it reported the following error when trying to access components.

RuntimeError                              Traceback (most recent call last)
<ipython-input-3-13e5ce6a4db2> in <module>()
----> 1 dma1=ol.axi_dma_0
      2 dma2=ol.axi_dma_1

/usr/local/lib/python3.6/dist-packages/pynq/overlay.py in __getattr__(self, key)
    325             return getattr(self._ip_map, key)
    326         else:
--> 327             raise RuntimeError("Overlay not currently loaded")
    328 
    329     def download(self):

RuntimeError: Overlay not currently loaded

From the error above, it seems I can’t access/manipulate it before really download the bitstream file again by “ol.download()”.
However, if I download the same bitstream again in the PYNQ Python script, I’m able to access the components we added but it seems it may interrupt some functions (for FMCOMMS) which have been working at that time in the system and then the operation with FMCOMMS may not behave as expected.

Maybe I misunderstand something here or something is still missing.
It would be great if you can give me some advice on it.
Thanks a lot.

1 Like
4

Can someone Please reply to above question?

5

You can manually reset the PL server after creating the overlay with download=False with the following line

pynq.Device.active_device.reset(ol.parser, ol.timestamp, ol.bitfile_name)

We’re looking at a better way of supporting this use-case in the next version.

Peter

1 Like