How to resolve timing violations in a Vivado design?

Support
1

Device: RFSoC 4x2 Kit
PYNQ Version: v3.0
I am working on a variant of an MTS project, but I encountered some issues.
Below are the screenshots of the problems I faced and my TCL file.
Any help would be greatly appreciated.

image
image554×205 38.7 KB

image
image554×151 54.8 KB

design.zip (33.0 KB)

2

Hi,

Did you check these forums about negative TNS?
(AMD Customer Community)
(Reddit - Dive into anything)

3

Hi @joe052790,

This question is outside of the scope of the PYNQ forum. You may be better off asking in the Xilinx forums.

Mario