Output getting filled with zero

Hi All,

I am using PYNQ Z2 v2.6 for accelerating an image processing algorithm. I noticed that my output buffer is filling with 0 or maybe my ip is not writing in these positions as specific. To be more specific, 4 indexes after every 4 elements (0,1,2,3 will be filled with the required value then 4,5,6,7 will be filled with 0 and then 8,9,10,11 with the required value and then again 12,13,14,15 with 0 and so on).

I suspected this might be because of my image processing logic happening. Therefore, I rewrote my custom ip logic as just taking input image and returning the same image as output without any processing of the image.

Still now I am seeing the same behaviour. I have hereby attached the output as well as the code below. The simulation works as required always but when moved into the PYNQ board it is not working as required. What could be the possible reason?

Can someone please help me? I am working on a time constraint project.

Custom Ip

void img_processing(ap_uint<8>* inp_stream, ap_uint<8>* output_stream, unsigned int rows, unsigned int cols){

	#pragma HLS INTERFACE m_axi port=inp_stream offset=slave bundle=gem1
	#pragma HLS INTERFACE m_axi port=output_stream offset=slave bundle=gem2
	#pragma HLS INTERFACE s_axilite port=rows offset=0x10
	#pragma HLS INTERFACE s_axilite port=cols offset=0x18
	#pragma HLS INTERFACE s_axilite port=return

	//defining all the required Mat
	xf::cv::Mat<XF_8UC1, MAX_HEIGHT, MAX_WIDTH, XF_NPPC1> in_mat(rows,cols);


	for (int i=0; i< (rows * cols); i++){
		in_mat.write(i, inp_stream[i]);

	for (int i=0; i< (rows * cols); i++){
		output_stream[i] = in_mat.read(i);

Python Code

from PIL import Image
from pynq import Overlay, allocate
import numpy as np

overlay = Overlay('edge_detection.bit')
regs = overlay.sobel_filter_0.register_map
sobel = overlay.sobel_filter_0

im = Image.open('./sobel.png')
im_gray = im.convert('L')

random_data = np.random.randint(0, 256, size=(10, 10), dtype=np.uint8)

buf_in = allocate(
	(10,10), np.uint8, cacheable=True )
buf_in[:] = random_data
buf_out = allocate(
	(10,10), np.uint8, cacheable=True )

regs.inp_stream_1 = buf_in.device_address
regs.output_stream_1 = buf_out.device_address
regs.rows = 10
regs.cols = 10




Hoping for a response soon !

Regards & Thanks in Advance,

Hi @srijith.krishnan,

How is the IP connected? What is the bit width of the HP port where the IP is connected?


Hi @marioruiz,

Thank you for the response !

The data width for HP port is 64 width and the addr width is 32. Just to confirm, the 64 here is bytes right?

IP Connection:

Data Width HP Port:


Hi, this is bits. You should change the data width of the HP port to 32-bit.

Hi @marioruiz ,

I tried changing the HP port to 32 bit but still I am seeing the same behaviour.

What is the bitwidth of gem ports in the IP?

@marioruiz, it was initially set to 64 bit but I changed them both to 32 bit. But still it is showing the same behaviour. The difference I see is that the protocol used for the gem ports are AXI3 and the protocol for HP port is AXI4.

Also @marioruiz , what is the difference between ‘ID Ports’ and ‘USER Ports’ here?

Where are you changing these values? This should be done in the Zynq 7000 IP

@marioruiz , The HP port width I changed them within the ZYNQ 7000 IP but the gem one I changed by double clicking the custom IP.

Can those also be changed within the ZYNQ ip? If so, Can you please guide me through?

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